Semiconductor structure having an anchor-shaped backside via
A semiconductor structure includes first and second source/drain (S/D) features, one or more channel layers connecting the first and the second S/D features, a high-k metal gate engaging the one or more channel layers, an isolation structure, a power rail under the isolation structure, and a via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail. At least a portion of the isolation structure is under the first and the second S/D features. In a cross-section that extends through the first S/D feature and perpendicular to a direction from the first S/D feature to the second S/D feature along the one or more channel layers, the via structure extends into a gap vertically between the first S/D feature and the isolation structure.
1. A semiconductor structure, comprising:
first and second source/drain (S/D) features;
one or more channel layers connecting the first and the second S/D features;
a high-k metal gate engaging the one or more channel layers;
an isolation structure, wherein at least a portion of the isolation structure is under the first and the second S/D features;
a power rail under the isolation structure; and
a via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail, wherein in a cross-section that extends through the first S/D feature and perpendicular to a direction from the first S/D feature to the second S/D feature along the one or more channel layers, the via structure extends into a gap vertically between the first S/D feature and the isolation structure.
2. The semiconductor structure of claim 1 , wherein in the cross-section, the via structure has a shape of an anchor.
3. The semiconductor structure of claim 1 , wherein in the cross-section, the semiconductor structure is free of a dielectric layer between the via structure and the isolation structure.
4. The semiconductor structure of claim 1 , wherein in the cross-section, a vertical dimension of the via structure inside the gap becomes smaller as the via structure extends towards a sidewall of the first S/D feature.
5. The semiconductor structure of claim 1 , further comprising a silicide layer between the via structure and the first S/D feature.
6. The semiconductor structure of claim 1 , wherein in the cross-section, the semiconductor structure further comprising a third S/D feature, wherein the first and the third S/D features are separated by a dielectric fin.
7. The semiconductor structure of claim 6 , wherein in the cross-section, the third S/D feature is electrically isolated from the power rail.
8. The semiconductor structure of claim 6 , wherein in the cross-section, the via structure directly contacts the dielectric fin.
9. The semiconductor structure of claim 6 , wherein in the cross-section, the semiconductor structure further comprising an air void between the via structure and the dielectric fin.
10. The semiconductor structure of claim 1 , wherein a vertical dimension of the gap is greater than 0.5 nm.
11. A semiconductor structure, comprising:
first and second source/drain (S/D) features;
one or more channel layers connecting the first and the second S/D features;
a high-k metal gate engaging the one or more channel layers;
a dielectric cap directly under the high-k metal gate;
an isolation structure, wherein at least a portion of the isolation structure is under the first and the second S/D features and the dielectric cap;
a power rail under the isolation structure; and
a via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail, wherein in a first cross-section that extends through the first S/D feature and perpendicular to a direction from the first S/D feature to the second S/D feature along the one or more channel layers, the via structure extends into a gap vertically between the first S/D feature and the isolation structure, thereby forming an anchor shape.
12. The semiconductor structure of claim 11 , wherein in a second cross-section that extends through the first S/D feature and perpendicular to the first cross-section, there is no gap vertically between the first S/D feature and the dielectric cap.
13. The semiconductor structure of claim 12 , further comprising a dielectric liner between the via structure and the isolation structure in the second cross-section.
14. The semiconductor structure of claim 13 , wherein the dielectric liner is not present between the via structure and the isolation structure in the first cross-section.
15. The semiconductor structure of claim 11 , further comprising a silicide layer between the via structure and the first S/D feature.
16. The semiconductor structure of claim 11 , further comprising two dielectric fins sandwiching the first S/D feature in the first cross-section.
17. The semiconductor structure of claim 16 , wherein the via structure directly contacts at least one of the dielectric fins.
18. A semiconductor structure, comprising:
first and second source/drain (S/D) features;
one or more channel layers connecting the first and the second S/D features;
a high-k metal gate engaging the one or more channel layers;
a dielectric cap directly under the high-k metal gate;
an isolation structure, wherein at least a portion of the isolation structure is under the first and the second S/D features and the dielectric cap;
a power rail under the isolation structure; and
a via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail, wherein in a first cross-section that extends through the first S/D feature and perpendicular to a direction from the first S/D feature to the second S/D feature along the one or more channel layers, the via structure extends into a gap vertically between the first S/D feature and the isolation structure, wherein in a second cross-section that extends through the first S/D feature and perpendicular to the first cross-section, there is no gap vertically between the first S/D feature and the dielectric cap.
19. The semiconductor structure of claim 18 , further comprising two dielectric fins sandwiching the first S/D feature in the first cross-section, wherein a vertical dimension of the via structure inside the gap becomes smaller as the via structure extends towards the dielectric fins in the first cross-section.
20. The semiconductor structure of claim 19 , wherein the via structure directly contacts at least one of the dielectric fins.