Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.
1. A method of manufacturing a semiconductor device, comprising, in a semiconductor on insulator (SOI) substrate having a compressively stressed buried insulator structure above a base silicon substrate and underneath a surface semiconductor layer, etching trenches through the surface semiconductor layer and the compressively stressed buried insulator structure and into the base silicon substrate in a pattern defined by a mask layer, thereby causing the compressively stressed buried insulator structure to extend outwards tensilely straining, in a nonuniform manner, the surface semiconductor layer across a portion of a lateral extent of the surface semiconductor layer between walls of the etched trenches, and forming said semiconductor device such that said semiconductor device has a channel region in an area of the surface semiconductor layer that is tensilely strained.
2. The method of manufacturing a semiconductor device of claim 1 , wherein the compressively stressed buried insulator structure comprises a buried oxide layer and a separate compressively strained buried stressor layer under the buried oxide layer.
3. The method of manufacturing a semiconductor device of claim 2 , wherein the compressively strained buried stressor layer extends throughout a wafer on which the semiconductor device is manufactured.
4. The method of manufacturing a semiconductor device of claim 2 , wherein the compressively strained buried stressor layer comprises polycrystalline silicon under compressive stress.
5. The method of manufacturing a semiconductor device of claim 4 , wherein the compressively strained buried stressor layer has an in-plane stress of magnitude greater than 200 megaPascal.
6. The method of manufacturing a semiconductor device of claim 4 , wherein the compressively strained buried stressor layer has an in-plane stress of magnitude greater than 1 gigaPascal.
7. The method of manufacturing a semiconductor device of claim 4 , wherein the trenches through the surface semiconductor layer and the compressively stressed buried insulator structure are etched to a depth deeper than a total thickness of the surface semiconductor layer and the stressed buried insulator structure of between about 300 nm and 400 nm.
8. The method of manufacturing a semiconductor device of claim 4 , further comprising prior to the etching of the trenches, depositing a material which forms the compressively strained buried stressor layer on both sides of the base silicon substrate, and after the etching of the trenches, etching the material off a back face of the base silicon substrate.
9. The method of manufacturing a semiconductor device of claim 2 , wherein the compressively strained buried stressor layer has an in-plane stress of magnitude greater than 200 megaPascal.
10. The method of manufacturing a semiconductor device of claim 2 , wherein the compressively strained buried stressor layer has an in-plane stress of magnitude greater than 1 gigaPascal.
11. The method of manufacturing a semiconductor device of claim 1 , wherein the trenches through the surface semiconductor layer and the compressively stressed buried insulator structure are etched to a depth deeper than a total thickness of the surface semiconductor layer and the stressed buried insulator structure of between about 300 nm and 400 nm.
12. The method of manufacturing a semiconductor device of claim 1 , further comprising prior to the etching of the trenches, depositing a material which forms the compressively strained buried stressor layer on both sides of the base silicon substrate, and after the etching of the trenches, etching the material off a back face of the base silicon substrate.
13. The method of manufacturing a semiconductor device of claim 1 , wherein the compressively stressed buried insulator structure is formed in part by depositing a layer of undoped amorphous silicon, doping the layer of undoped amorphous silicon by ion implantation to form a layer of doped amorphous silicon, and then subsequently annealing to convert the layer of doped amorphous silicon to a layer of doped polycrystalline silicon.
14. The method of manufacturing a semiconductor device of claim 1 , wherein the compressively stressed buried insulator structure includes polycrystalline silicon.