Communication between stacked die
In a stacked integrated circuit device, there are two components, one in a first of the die and another in a second of the die. Each of the components is provided with two output connections, one leading above and one leading below the die, and two input connections, one leading above and one leading below the die, either of the two die. As a result of the redundancy, both die may be used in either position in the stacked structure. If either of the die is used as the top die, it sends data on its second output path and receives data on its second input path. On the other hand, when one of the die is used as the bottom die, it sends data on its first output path and receives data on its first input path. In this way, the same design may be used for the connections between each of the die.
1 . A stacked integrated circuit device comprising a plurality of die, wherein each of two or more of the plurality of die comprises:
a plurality of metal layers;
a component; and
a plurality of connections associated with the component, the plurality of connections comprising:
a first input path connecting to a top of the plurality of metal layers of a respective die;
a second input path connected to a bottom of the plurality of metal layers of the respective die;
a first output path connected to the top of the plurality of metal layers of the respective die;
a second output path connected to the bottom of the plurality of metal layers of the respective die;
wherein for a first die of the two or more die:
the first input path is unconnected to a further one of the two or more die, so as to be inoperable for receiving data from any of the two or more die;
the second input path provides a connection to the second die for receiving data from the component of the second die;
the first output path is unconnected to a further one of the two or more die, so as to be inoperable for sending data to any of the two or more die; and
the second output path provides a connection to the second die for sending data from the component of the first die to the second die;
wherein for a second die of the two or more die:
the first input path provides a connection to the first die for receiving data from the component of the first die;
the second input path is unconnected to a further one of the two or more die, so as to be inoperable for receiving data from any of the two or more die;
the first output path provides a connection to the first die for sending data from the component of the second die to the first die; and
the second output path is unconnected to a further one of the two or more die, so as to be inoperable for sending data to any of the two or more die.
2 . The stacked integrated circuit device of claim 1 , wherein each of the two or more die comprises an output bus associated with the component of the respective die and connected to the first output path and the second output path of the respective die, wherein each of the components is operable to broadcast data to others of the two or more die by transmitting that broadcast data on its output bus.
3 . The stacked integrated circuit device of claim 1 , wherein each of the two or more die comprises a multiplexer controlled by a die identifier signal for the respective die, so as to select between the respective first input path and the respective second input path.
4 . The stacked integrated circuit device of claim 1 , wherein each of the two or more die comprises a multiplexer controlled by a die identifier signal for the respective die, so as to select between the respective first output path and the respective second output path.
5 . The stacked integrated circuit device of claim 4 , wherein each of the two or more die comprises one of a plurality of circuits and each of the circuits is configured to:
receive a first signal for the respective die, the first signal for the respective die being received from a source external to the respective die; and
modify the first signal to produce a second signal for the respective die,
wherein for each of the two or more die, the die identifier signal for that die is one of:
the respective first signal received by the circuit of that die; or
the second signal output by the circuit of that die.
6 . The stacked integrated device of claim 5 , wherein each of the circuits comprises an invertor.
7 . The stacked integrated circuit of claim 5 , wherein the plurality of die comprises a further die connected to the top surface of the first die, wherein the circuit of the first die is configured to receive the first signal for the first die from the further die.
8 . The stacked integrated circuit device of claim 1 , wherein the two or more die comprises a third die provided between the first die and the second die, wherein for the third die:
the first input path provides a connection to the first die for receiving data from the first die;
the second input path provides a connection to the second die for receiving data from the second die;
the first output path provides a connection to the first die for sending data to the first die; and
the second output path provides a connection to the second die for sending data to the second die.
9 . The stacked integrated circuit device of claim 8 , wherein the plurality of connections further comprises:
a third input path connected to the top metal layer of the respective die; and
a fourth input path connected to the bottom metal layer of the respective die,
wherein for the first die, the fourth input path is used for receiving data from the component of the third die,
wherein for the second die, the third input path is used for receiving data from the component of the third die.
10 . The stacked integrated circuit device of claim 1 , wherein, for each of the two or more die, the plurality of connections are provided in a same layout.
11 . The stacked integrated circuit device of claim 1 , wherein for the first die, the second input path is connected to the component of the first die for providing data to the component of the first die from the component of the second die, wherein for the second die, the first input path is connected to the component of the second die for providing data to the component of the second die from the component of the first die.
12 . The stacked integrated circuit device of claim 1 , wherein the first die and the second die each comprise a multi-tile processor, wherein for the first die and the second die:
the respective component is one of the tiles of the multi-tile processor of that die; and
each of the tiles of the multi-tile processor of that die is associated with an instance of the plurality of connections enabling it to communicate with another of the first die and the second die.
13 . The stacked integrated circuit device of claim 1 , wherein each of the two or more die comprises a multiplexer configured to select between outputting data from another of the two or more die or the component of the respective die to which it belongs,
wherein the multiplexer of the first die is configured to receive the second input path as input,
wherein the multiplexer of the second die is configured to receive the first input path as an input.
14 . The stacked integrated circuit device of claim 13 , wherein each of the multiplexers is configured to outputs the data to a switching fabric of the respective die.
15 . The stacked integrated circuit device of claim 13 , wherein each of the multiplexers is configured to be controlled to select between outputting data from another of the two or more die or the component of the respective die to which it belongs in dependence upon control signals received from each of the components.
16 . The stacked integrated circuit device of claim 1 , wherein for each of the two or more die, the plurality of connections are arranged such that:
a position of the first input path at the top surface of the respective die is aligned horizontally with a position corresponding to an end of the second output path at the bottom metal layer of the respective die; and
a position of the first output path at the top surface of the respective die is aligned horizontally with a position of the second input path at the bottom metal layer of the respective die.
17 . An integrated circuit device comprising:
a first die in a stacked arrangement with a second die, the first die comprising a first plurality of metal layers, a first component, and a first plurality of connections associated with the first component, the first plurality of connections comprising:
a first input path connecting to a top of the first plurality of metal layers, wherein the first input path is unconnected to the second die, so as to be inoperable for receiving data from the second die;
a second input path connected to a bottom of the first plurality of metal layers, wherein the second input path is configured to provide a connection to the second die for receiving data from a second component of the second die;
a first output path connected to the top of the first plurality of metal layers, wherein the first output path is unconnected to the second die, so as to be inoperable for sending data to the second die; and
a second output path connected to the bottom of the first plurality of metal layers, wherein the second output path is configured to connect to the second die for sending data from the first component to the second die;
wherein the second die comprises:
a third input path configured to connect to the first die for receiving data from the first component;
a fourth input path that is unconnected to the first die, so as to be inoperable for receiving data from the first die;
a third output path configured to connect to the first die for sending data from the second component to the first die; and
a fourth output path that is unconnected to the first die, so as to be inoperable for sending data to the first die.
18 . The integrated circuit device of claim 17 , wherein the first die comprises an output bus associated with the first component and connected to the first output path and the second output path, wherein the first component is configured to broadcast data on the output bus.
19 . The integrated circuit device of claim 17 , wherein the first die comprises:
a first multiplexer controlled by a die identifier signal for the first die, so as to select between the first output path and the second output path; and
a second multiplexer controlled by the die identifier signal, so as to select between the first input path and the second input path.
20 . The integrated circuit device of claim 19 , wherein the first die comprises an invertor that is configured to:
receive a first signal for the first die, the first signal for the first die being received from a source external to the first die; and
modify the first signal to produce a second signal for the first die, wherein the die identifier signal comprises the first signal or the second signal.
21 . The integrated circuit device of claim 20 , further comprising:
a third die connected to a top surface of the first die, wherein the first component is configured to receive the first signal from the third die.
22 . The integrated circuit device of claim 17 , further comprising a third die in the stacked arrangement between the first die and the second die, wherein the third die comprises:
a fifth input path configured to connect to the first die for receiving data from the first die;
a sixth input path configured to connect to the second die for receiving data from the second die;
a fifth output path configured to connect to the first die for sending data to the first die; and
a sixth output path configured to connect to the second die for sending data to the second die.
23 . The integrated circuit device of claim 17 , wherein for the first die, the second input path is connected to the first component for providing data to the first component from the second processor component, wherein for the second die, the third input path is connected to the second component for providing data to the second component from the first component.
24 . The integrated circuit device of claim 17 , wherein the first component is a multi-tile processor having a plurality of tiles, each of the tiles of the multi-tile processor being associated with an instance of the first plurality of connections to communicate with the second die.
25 . The integrated circuit device of claim 17 , wherein the first die comprises a first multiplexer configured to select between outputting data from the second die or outputting data from the first component, wherein the first multiplexer is configured to receive the second input path as input,
wherein the second die comprises a second multiplexer configured to select between outputting data from the first die or outputting data from the second component, wherein the second multiplexer is configured to receive the third input path as an input.
26 . The integrated circuit device of claim 25 , wherein the first multiplexer and the second multiplexer are configured to output data to a switching fabric.
27 . The integrated circuit device of claim 17 , wherein for the first die, the first plurality of connections are arranged such that:
a position of the first input path at a top surface of the first die is aligned horizontally with a position corresponding to an end of the second output path at a bottom metal layer of the first die; and
a position of the first output path at the top surface of the first die is aligned horizontally with a position of the second input path at the bottom metal layer of the first die.