Memory scaling semiconductor device
A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.
1. An integrated memory module comprising:
a first semiconductor die, comprising:
a first memory array,
a first substrate next to the first memory array, and
a first surface having a first group of bond pads; and
a second semiconductor die, comprising:
a second memory array,
a second substrate next to the second memory array, and
a second surface having a second group of bond pads;
wherein the integrated memory module is configured to avoid warping by bonding the first and second semiconductor dies together, first surface to second surface; and
wherein the first substrate is thinner than the first memory array.
2. The integrated memory module of claim 1 , wherein the first and second groups of bond pads are bonded together to electrically couple the first and second semiconductor dies to each other.
3. The integrated memory module of claim 1 , further comprising:
a third surface in the first semiconductor die opposite the first surface,
a third group of bond pads formed in the third surface, the third group of bond pads configured to electrically connect the integrated memory module to a host device, and
electrical connections formed between the first group of bond pads and the third group of bond pads in the first semiconductor die.
4. The integrated memory module of claim 3 , wherein the electrical connections, the first group of bond pads and the second group of bond pads allow the first semiconductor die to be electrically accessed by a host device independently of the second semiconductor die, the second semiconductor die to be electrically accessed independently of the first semiconductor die, or the first and second semiconductor dies to be electrically accessed as a single unit.
5. The integrated memory module of claim 3 , wherein the electrical connections comprise a first set of vias physically connected to the first group of bond pads at the first surface.
6. The integrated memory module of claim 5 , wherein the electrical connections comprise a second set of vias physically connected to the third group of bond pads at the third surface.
7. The integrated memory module of claim 3 , wherein memory module is configured to be stacked in an offset stepped configuration and packaged together with other memory modules that are wire bonded together using the third set of bond pads.
8. The integrated memory module of claim 3 , wherein the electrical connections comprise a first set of electrical connections, the integrated memory module further comprising:
a fourth surface in the second semiconductor die opposite the second surface,
a fourth group of bond pads formed in the fourth surface, the fourth group of bond pads configured to electrically connect the integrated memory module to a host device, and
a second set of electrical connections formed between the second group of bond pads and the fourth group of bond pads in the second semiconductor die.
9. The integrated memory module of claim 8 , wherein the second set of electrical connections comprise a third set of vias physically connected to the second group of bond pads at the second surface.
10. The integrated memory module of claim 9 , wherein the second set electrical connections comprise a fourth set of vias physically connected to the fourth group of bond pads at the fourth surface.
11. The integrated memory module of claim 10 , wherein memory module is configured to be stacked in an overlapped configuration and packaged together with other memory modules that are electrically coupled to each other by the first, second, third and fourth sets of vias through the first and second semiconductor dies.
12. The integrated memory module of claim 1 , wherein the second substrate is thinner than the second memory array.
13. An integrated memory module comprising:
a first semiconductor die, comprising:
a first memory array formed in a first surface of the first semiconductor die,
a first substrate next to the first memory array
a first group of bond pads formed in the first surface of the first semiconductor die,
a second surface opposite the first surface,
a second group of bond pads formed in the second surface, and
electrical connections formed between the first group of bond pads and the second group of bond pads in the first semiconductor die; and
a second semiconductor die, comprising:
a second memory array formed in a third surface of the second semiconductor die,
a second substrate next to the second memory array, and
a third group of bond pads formed in the third surface of the second semiconductor die, the first and third groups of bond pads bonded to each other;
wherein memory module is configured to be stacked in an offset stepped configuration and packaged together with other memory modules that are wire bonded together using the second set of bond pads.
14. The integrated memory module of claim 13 , wherein the electrical connections comprise a first set of electrical connections, the integrated memory module further comprising:
a fourth surface in the second semiconductor die opposite the third surface,
a fourth group of bond pads formed in the fourth surface, the fourth group of bond pads configured to electrically connect the integrated memory module to a host device, and
a second set of electrical connections formed between the third group of bond pads and the fourth group of bond pads in the second semiconductor die.
15. The integrated memory module of claim 14 , wherein the second set of electrical connections comprise a third set of vias physically connected to the second group of bond pads at the second surface.
16. The integrated memory module of claim 15 , wherein the second set electrical connections comprise a fourth set of vias physically connected to the fourth group of bond pads at the fourth surface.