3D integrated circuit device fabrication using interface wafer as permanent carrier

1. A method for fabricating a 3D integrated circuit, the method comprising the steps of:

providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias;

providing a first active circuitry layer wafer including active circuitry and through-silicon vias;

bonding the first active circuitry layer wafer face down to the interface wafer;

after bonding the first active circuitry layer wafer face down to the interface wafer, removing a first portion of the first active circuitry layer wafer such that a second portion of the first active circuitry layer wafer remains attached to the interface wafer;

after removing the first portion of the first active circuitry layer wafer, fabricating a second wiring layer on the second portion of the first active circuitry layer wafer;

providing a second active circuitry layer wafer including active circuitry;

bonding the second active circuitry layer wafer face down to the second wiring layer;

after bonding the second active circuitry layer wafer face down to the second wiring layer, removing a first portion of the second active circuitry layer wafer such that a second portion of the second active circuitry layer wafer remains attached to the second wring layer;

after removing the first portion of the second active circuitry layer wafer, fabricating a third wiring layer on the second portion the second active circuitry layer wafer;

providing a base wafer, the base wafer including a fourth wiring layer;

bonding the third wiring layer face down to the base wafer;

after bonding the third wiring layer face down to the base wafer, thinning the interface wafer so as to form an interface layer, and forming metallizations comprising solder bumps on the interface layer, the solder bumps being coupled through the through-silicon vias in the interface layer to the first wiring layer; and

bonding the solder bumps to a package.

2. A method for fabricating a 3D integrated circuit structure, the method comprising the steps of:

providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias;

providing a first active circuitry layer wafer including active circuitry;

bonding the first active circuitry layer wafer face down to the interface wafer;

after bonding the first active circuitry layer wafer, removing a first portion of the first active circuitry layer wafer such that a second portion of the first active circuitry layer wafer remains attached to the interface wafer;

providing a base wafer, the base wafer including a second wiring layer;

bonding a stack structure face down to the base wafer, the stack structure including the interface wafer and the second portion of the first active circuitry layer wafer; and

after bonding the stack structure, thinning the interface wafer so as to form an interface layer, and forming metallizations on the interface layer, the metallizations being coupled through the through-silicon vias in the interface layer to the first wiring layer.

3. The method of claim 2 , further comprising the steps of:

providing another active circuitry layer wafer including active circuitry;

bonding the other active circuitry layer wafer face down above the interface wafer and the second portion of the first active circuitry layer wafer; and

after bonding the other active circuitry layer wafer, removing a first portion of the other active circuitry layer wafer such that a second portion of the other active circuitry layer wafer remains above the interface wafer and the second portion of the first active circuitry layer wafer,

wherein the stack structure that is bonded face down to the base wafer also includes the second portion of the other active circuitry layer wafer.

4. The method of claim 3 , further comprising the step of:

repeating N times the steps of providing another active circuitry layer wafer, bonding the other active circuitry layer wafer, and removing a first portion of the other active circuitry layer wafer,

wherein the stack structure that is bonded face down to the base wafer also includes the second portions of the N other active circuitry layer wafers.

5. The method of claim 3 , further comprising the steps of:

after removing the first portion of the other active circuitry layer wafer, fabricating another wiring layer on the second portion of the other active circuitry layer wafer; and

repeating N times the steps of providing another active circuitry layer wafer, bonding the other active circuitry layer wafer, removing a first portion of the other active circuitry layer wafer, and fabricating another wiring layer,

wherein in the step of bonding the stack structure face down to the base wafer, the wiring layer on the second portion of the Nth wafer is bonded face down to the base wafer.

6. The method of claim 3 , further comprising the steps of:

after removing the first portion of the first active circuitry layer wafer, fabricating a third wiring layer on the second portion of the first active circuitry layer wafer; and

after removing the first portion of the other active circuitry layer wafer, fabricating a fourth wiring layer on the second portion of the other active circuitry layer wafer,

wherein in the step of bonding the other active circuitry layer wafer, the other active circuitry layer wafer is bonded face down to the third wiring layer, and

in the step of bonding the stack structure, the fourth wiring layer is bonded face down to the base wafer.

7. The method of claim 2 , further comprising the step of:

after removing the first portion of the first active circuitry layer wafer, fabricating a third wiring layer on the second portion of the first active circuitry layer wafer,

wherein in the step of bonding the stack structure, the third wiring layer is bonded face down to the base wafer.

8. The method of claim 2 , wherein the interface wafer is formed of a material that is not soluble in an etchant used in the removing step to remove the first portion of the first active circuitry layer wafer.

9. The method of claim 2 , wherein the metallizations on the interface layer comprise solder bumps.

10. The method of claim 2 , wherein the first active circuitry layer wafer comprises a bulk silicon wafer.