Enhanced subtractive etch anisotropy using etch rate gradient
Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.
1 . A package substrate, comprising:
a core comprising insulative material;
first conductive traces in contact with a surface of the core; and
buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material,
wherein:
the first conductive traces comprise at least a first metal and a second metal,
the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region,
a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and
the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.
2 . The package substrate of claim 1 , wherein the relative concentration of the first metal to the second metal between the first region and the second region decreases with increasing distance from the core.
3 . The package substrate of claim 1 , wherein:
the first conductive traces have respective surfaces distant from and parallel to the core,
the respective surfaces are at an orthogonal distance from the core, and
a lateral distance between the surfaces of adjacent ones of the first conductive traces is approximately less than twice the orthogonal distance.
4 . The package substrate of claim 1 , wherein the first region comprises approximately 100% of the first metal and 0% of the second metal, and the second region comprises approximately 5% of the first metal and 95% of the second metal.
5 . The package substrate of claim 1 , wherein:
any one of the first conductive traces has:
a top surface distant from and parallel to the core; and
sidewalls not parallel to or coplanar with the top surface,
the top surface is an interface between the second region and the buildup layers,
the sidewalls are between the core and the top surface with the core being on one side and the top surface being on an opposite side of the respective sidewalls, and
respective contours of the sidewalls vary according to a gradient of the relative concentration of the first metal to the second metal between the first region and the second region.
6 . The package substrate of claim 1 , wherein:
the first metal has a first etch rate with an etchant,
the second metal has a second etch rate with the etchant, and
the first etch rate is greater than the second etch rate.
7 . The package substrate of claim 6 , wherein:
the etchant is an alkali,
the first metal is copper, and
the second metal comprises at least one selected from a group comprising: nickel, iron, bismuth, lead, and tin.
8 . The package substrate of claim 6 , wherein:
the etchant is an acid,
the first metal is copper, and
the second metal comprises a material that is resistant to etching by the acid.
9 . A microelectronic assembly, comprising:
a package substrate having a core, and conductive traces and buildup layers on either side of the core; and
an integrated circuit (IC) die coupled to one of the buildup layers of the package substrate,
wherein:
the conductive traces comprise at least a first metal and a second metal in a non-uniform distribution across a thickness of the conductive traces,
a relative concentration of the first metal to the second metal is greater proximate to the core, and
the relative concentration of the first metal to the second metal decreases with increasing distance from the core.
10 . The microelectronic assembly of claim 9 , wherein a space between adjacent conductive traces is approximately equal to the thickness of the conductive traces.
11 . The microelectronic assembly of claim 9 , wherein a shape of surfaces of the conductive traces not parallel to the sides of the core varies according to the relative concentration of the first metal to the second metal.
12 . The microelectronic assembly of claim 11 , wherein:
the surfaces are steeper in a second region than in a first region, and
the relative concentration of the first metal to the second metal in the second region is smaller than in the first region.
13 . The microelectronic assembly of claim 9 , wherein:
the first metal is copper, and
the second metal comprises a selection from: nickel, gold, titanium, bismuth, lead and tin.
14 . The microelectronic assembly of claim 9 , wherein an etchant has selective affinity for the first metal over the second metal such that an etch rate of the first metal with the etchant is greater than of the second metal with the etchant.
15 . The microelectronic assembly of claim 14 , wherein the second metal is inert to the etchant.
16 . A method, comprising:
providing a core of a package substrate, the core comprising a layer of conductive material over a substrate material, the layer having a thickness, the conductive material comprising at least a first metal and a second metal distributed non-uniformly with a relative concentration of the first metal to the second metal being greater proximate to the substrate material than distant from the substrate material;
attaching a mask over the layer of conductive material, the mask comprising a pattern of conductive traces; and
etching the layer of conductive material with an etchant, the etchant being selective to the first metal over the second metal such that the conductive material is removed according to the pattern of the mask and a lateral distance between two adjacent conductive traces is approximately less than twice the thickness of the layer.
17 . The method of claim 16 , wherein:
the first metal is not inert to the etchant, and
the second metal is inert to the etchant.
18 . The method of claim 16 , wherein:
the etchant is an acid, and
the mask comprises an organic dielectric material.
19 . The method of claim 16 , wherein:
the etchant is an alkali, and
the mask comprises a metal resistant to etching by the alkali.
20 . The method of claim 16 , wherein etching the layer of conductive material comprises anisotropic etching, with an etching rate is slower proximate to the mask, and faster distant from the mask, proximate to the substrate material such that the anisotropic etching has a preferential downward direction toward the substrate material.