Granted Patent B2

US 12,578,984 · App. 17/942,558 · Granted Mar 17, 2026

Inventor: Steven Jeffrey Wallach (Dallas, TX)

Assignee: Micron Technology, Inc.

G06F9/45558G06F2009/45562G06F2009/45579G06F2009/45583G06F2009/45587

Abstract

Claims (60)

1 . A device, comprising:

a processor, having:

at least one execution unit;

a memory management unit; and

a virtual machine register;

wherein the processor is configured to:

execute at least one instruction in a domain of a plurality of domains, wherein each of the plurality of domains is associated with a distinct set of one or more address translation tables;

store, in the virtual machine register, an identifier of a virtual machine for which the processor is executing the at least one instruction in the domain;

implement a computing resource restriction for the virtual machine based on the identifier, wherein the computing resource restriction restricts the virtual machine to resources associated with the domain;

execute, in response to trapping an operation performed during execution of a program executing in the virtual machine, a routine to identify a physical address page of a memory corresponding to a pseudo-physical address page in the virtual machine;

determining a first base of an address translation table associated with the domain;

combining the first base and the identifier of the virtual machine to generate a second base of an address translation table associated with the domain; and

translating, using the memory management unit, virtual memory addresses used by the at least one instruction to physical memory addresses of a memory using the second base.

2 . The device of claim 1 , further comprising:

the memory having physical memory addresses.

3 . The device of claim 1 , wherein the base of address translation table is a second base of address translation table, and the processor is further configured to:

store, in the memory management unit, entries of address translation tables;

determine a first base of address translation table via selection of the first base from a plurality of candidates;

combine the first base and the identifier of the virtual machine to generate the second base of address translation table; and

translate, using the memory management unit, virtual memory addresses used by instructions of the virtual machine to physical memory addresses using the second base.

4 . The device of claim 3 , wherein the processor is further configured to confine an operating system executed on the virtual machine to a portion of memory provisioned to the virtual machine.

5 . The device of claim 3 , wherein the processor is further configured to select the first base from the plurality of candidates configured for a current domain of routines.

6 . The device of claim 3 , wherein the processor is configured to convert pseudo-physical addresses used in the virtual machine to physical addresses in the memory based on the identifier stored in the virtual machine register.

7 . The device of claim 3 , wherein the processor is configured to use a portion of a virtual address to generate an index to access an entry in an address translation table.

8 . The device of claim 7 , wherein the processor is configured to hash a combination of the portion of the virtual address and the identifier to generate the index.

9 . The device of claim 8 , wherein the portion of the virtual address includes an object identifier specified in the virtual address.

10 . A method, comprising:

storing, in a virtual machine register configured in a processor having at least one execution unit, an identifier of a virtual machine having at least one instruction being executed by the at least one execution unit at a time the identifier is stored in the virtual machine register;

executing at least one instruction in a domain of a plurality of domains, wherein each of the plurality of domains is associated with a distinct set of one or more address translation tables;

implementing, by utilizing the processor, a computer resource restriction for the virtual machine based on the identifier, wherein the computing resource restriction restricts the virtual machine to resources associated with the domain;

executing, in response to trapping an operation performed during execution of a program executing in the virtual machine, a routine to identify a physical address page of a memory corresponding to a pseudo-physical address page in the virtual machine;

determining a first base of an address translation table associated with the domain;

combining the first base and the identifier of the virtual machine to generate a second base of an address translation table associated with the domain; and

translating, using the memory management unit, virtual memory addresses used by the at least one instruction to physical memory addresses of a memory using the second base.

11 . The method of claim 10 , further comprising:

selecting the first base from a plurality of candidates.

12 . The method of claim 11 , further comprising:

confining an operating system executed on the virtual machine to a portion of the memory provisioned to the virtual machine.

13 . The method of claim 11 , wherein the plurality of candidates are configured for a current domain of routines.

14 . The method of claim 10 , further comprising:

converting pseudo-physical addresses used in the virtual machine to physical addresses in the memory based on the identifier stored in the virtual machine register.

15 . The method of claim 10 , further comprising:

generating, using a portion of a virtual address, an index to access an entry in an address translation table.

16 . The method of claim 15 , further comprising:

hashing a combination of the portion of the virtual address and the identifier to generate the index.

17 . The method of claim 16 , wherein the portion of the virtual address includes an object identifier specified in the virtual address.

18 . An apparatus, comprising:

a memory;

a memory management unit configured to store entries of address translation tables and perform address translation using the address translation tables;

at least one execution unit; and

a register configured to store an identifier of a virtual machine having instructions loaded from the memory for execution in the at least one execution unit at a time the identifier is stored in the register;

wherein the apparatus is configured to:

execute at least one instruction in a domain of a plurality of domains, wherein each of the plurality of domains is associated with a distinct set of one or more address translation tables;

implement a computing resource restriction for the virtual machine based on the identifier, wherein the computing resource restriction restricts the virtual machine to resources associated with the domain;

execute, in response to trapping an operation performed during execution of a program executing in the virtual machine, a routine to identify a physical address page of a memory corresponding to a pseudo-physical address page in the virtual machine;

determine a first base of an address translation table including a mapping of the physical address page to a virtual address page of the virtual machine associated with the domain;

combine the first base and the identifier of the virtual machine to generate a second base of an address translation table associated with the domain; and

translate, using the memory management unit, virtual memory addresses used by the instructions to physical memory addresses using the second base.

19 . The apparatus of claim 18 , wherein the memory management unit is configured to hash a combination of the identifier stored in the register and a portion of a first virtual memory address to generate an index and apply the index to locate a page table entry to translate the first virtual memory address to a physical memory address in the memory.

20 . The apparatus of claim 19 , wherein the apparatus is further configured to convert a page table entry mapping the physical address page to the virtual address page.

Assignments (1)

Continuity (8)

References Cited (208)