Granted Patent B2

US 12,242,653 · App. 17/511,756 · Granted Mar 4, 2025

Inventor: Steven Jeffrey Wallach (Dallas, TX)

Assignee: Micron Technology, Inc.

G06F21/629

Abstract

Claims (49)

1. A processor, comprising:

a logic circuit configured to execute instructions retrieved from a memory; and

a plurality of registers, wherein the processor is operable to store, in the plurality of registers respectively, locations of a plurality of domain access tables, each respective domain access table in the plurality of domain access tables associated with a respective domain among a predefined set of domains of instructions loadable from the memory for execution in the logic circuit, the respective domain access table having one or more entries configured to identify one or more entry points of the respective domain;

a first register configured to store an identifier of a current domain among the predefined set of domains, wherein instructions of a routine currently being executed in the processor are classified to be in the current domain;

wherein in response to a transition of instruction execution from a first domain, among the plurality of domains of instructions, to a second domain different from the first domain, the processor is configured to validate a permission to enter the second domain using data specified for an entry point in a domain access table associated with the second domain;

wherein in response to an instruction configured to request crossing of instruction execution from the current domain to a destination domain, the process is configured to update the first register to store an identifier of the destination domain specified in the instruction;

wherein in response to the instruction, the processor is configured to determine, whether to isolate resources of a calling routine and a called routine.

2. The processor of claim 1 , wherein the logic circuit includes a plurality of execution units.

3. The processor of claim 2 , further comprising:

a plurality of stacks configured for respective domains in the predefined set, wherein the processor is configured to use a corresponding stack, among the plurality of stacks, according to the first register.

4. The processor of claim 3 , further comprising:

a plurality of register value regions configured to store values of control registers for the respective domains in the predefined set;

wherein the control registers include at least one of a program counter (PC), a stack pointer (SP), a frame pointer (FP), an argument pointer (AP), or a processor status word (PSW), or any combination thereof.

5. The processor of claim 2 , wherein in response to the instruction, the processor is configured to control, based on a permission specified for a domain identified by the first register, access to a memory region during execution of the instruction.

6. The processor of claim 2 , wherein in response to the instruction, the processor is configured to determine, based on a permission specified for a domain identified by the first register, whether to isolate resources of a calling routine and a called routine.

7. The processor of claim 2 , wherein the instruction includes the identifier of the destination domain and an entry index; and the processor is configured to determine whether transition from the current domain to the destination domain is permitted according to data retrieved from a first domain access table using the entry index.

8. The processor of claim 2 , wherein the instruction includes the identifier of the destination domain and an entry index; and the processor is configured to identify a first domain access table using the identifier of the destination domain and determine whether transition from the current domain to the destination domain is permitted by applying to the entry index to the first domain access table.

9. The processor of claim 8 , wherein the processor is configured to determine whether transition from the current domain to the destination domain is permitted based on a bound check on the entry index using a count of entries in the first domain access table.

10. The processor of claim 8 , wherein the processor is configured to determine whether transition from the current domain to the destination domain is permitted based on a bit in an entry in the first domain access table, the entry identified by the entry index specified in the instruction, and the bit identified using the identifier of the current domain.

11. A method, comprising:

storing, in a plurality of registers of a processor, data representative of locations of a plurality of domain access tables, each respective domain access table in the plurality of domain access tables associated with a respective domain among a predefined set of domains of instructions loadable from memory for execution in the processor, the respective domain access table having one or more entries configured to identify one or more entry points of the respective domain;

storing, in a first register of the processor, an identifier of a current domain among the predefined set of domains, wherein instructions of a first routine currently being executed in the processor are classified to be in the current domain;

receiving in the processor a first instruction of the first routine for execution, the first instruction containing an identifier of a destination domain among the predefined set of domains and configured to call a second routine having a second instruction in the destination domain, the first instruction further containing an entry index; and

in response to the first instruction:

identifying, by the processor based on the identifier of the destination domain specified in the first instruction and the locations identified by the plurality of registers, a first domain access table;

determining, by the processor based on an entry identified by the entry index in the first domain access table, whether a transition from instruction execution in the current domain to instruction execution in the destination domain is permitted; and

determining, by the processor, whether the transition is permitted based on a bound check on the entry index according to a count of entries in the first domain access table.

12. The method of claim 11 , further comprising:

retrieving, by the processor from the first domain access table, the entry identified by the entry index; and

determining, by the processor, a bit in the entry according to the identifier of the current domain, wherein whether the transition is permitted is based at least in part on the bit identified for the current domain in the entry.

13. The method of claim 12 , further comprising:

determining, by the processor based on the entry, an address of the second instruction in the destination domain.

14. The method of claim 13 , further comprising:

updating, by the processor in response to a determination that the transition is permitted, the first register to store the identifier of the destination domain specified in the first instruction.

15. The method of claim 12 , further comprising:

determining, by the processor based on the entry, whether to isolate resources of the first routine containing the first instruction and the second routine called by the first instruction.

16. A computer, comprising:

memory configured to store instructions of routines; and

a processor coupled to the memory, the processor having:

a plurality of execution units;

a plurality of registers operable to store data representative of locations of a plurality of domain access tables, each respective domain access table in the plurality of domain access tables associated with a respective domain among a predefined set of domains of instructions loadable from the memory for execution in the plurality of execution units, the respective domain access table having one or more entries configured to identify one or more entry points of the respective domain;

a first register operable to store an identifier of a current domain among the predefined set of domains, wherein instructions of a first routine currently being executed in the processor are classified to be in the current domain;

wherein in response to a first instruction the first routine being loaded in the processor for execution, the processor is configured to:

identify, based on an identifier of a destination domain specified in the first instruction and the locations identified by the plurality of registers, a first domain access table; and

determine, based on an entry identified by the entry index in the first domain access table, whether a transition from instruction execution in the current domain to instruction execution in the destination domain is permitted;

wherein the processor is further configured to determine whether the transition is permitted based on a bound check on the entry index according to a count of entries in the first domain access table, and a bit identified in the entry according to the identifier of the current domain.

17. The computer of claim 16 , wherein the processor is further configured to determine, based on the entry:

an address of a second instruction of a second routine in the destination domain; and

whether to isolate resources of the first routine containing the first instruction and the second routine called by the first instruction.

Assignments (1)

Continuity (7)

References Cited (189)

Cited By (2)

US 12,578,984 US 12,717,902