IP Library › Granted Patent US 12,538,810
Granted Patent B2
US 12,538,810 · App. 17/944,657 · Granted Jan 27, 2026

Molded package having an electrically conductive clip with a convex curved surface attached to a semiconductor die

Inventors: Wee Aun Jason Lim (Melaka, MY); Marie Hazel Barozzo Gabrillo (Villach, AT); Chai Chee Lee (Melaka, MY); Nor Haqimi Mohamed (Melaka, MY)
Assignee: Infineon Technologies AG
H01L23/49548H01L21/4825H01L21/4842H01L21/56H01L23/3107H01L23/49517H01L24/32H01L2224/32245
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Quick Facts
Patent No.
US 12,538,810
App. No.
17/944,657
Granted
Jan 27, 2026
Kind
B2
Abstract

A molded package includes: a semiconductor die; a substrate attached to a bottom side of the semiconductor die; an electrically conductive clip attached to a top side of the semiconductor die; and a mold compound encapsulating the semiconductor die. A top side of the electrically conductive clip faces away from the semiconductor die and has an exposed flat surface that overlays the semiconductor die and is not covered by the mold compound. A bottom side of the electrically conductive clip faces the semiconductor die and has a convex curved surface that is attached to the top side of the semiconductor die. Along a vertical cross-section of the electrically conductive clip from the exposed flat surface to the convex curved surface, the electrically conductive clip has a plano-convex shape delimited by the exposed flat surface and the convex curved surface. A method of producing the molded package is also described.

Claims (29)

1 . A molded package, comprising:

a semiconductor die;

a substrate attached to a bottom side of the semiconductor die;

an electrically conductive clip attached to a top side of the semiconductor die; and

a mold compound encapsulating the semiconductor die,

wherein a top side of the electrically conductive clip faces away from the semiconductor die and has an exposed flat surface that overlays the semiconductor die and is not covered by the mold compound,

wherein a bottom side of the electrically conductive clip faces the semiconductor die and has a convex curved surface that is attached to the top side of the semiconductor die,

wherein along a vertical cross-section of the electrically conductive clip from the exposed flat surface to the convex curved surface, the electrically conductive clip has a plano-convex shape delimited by the exposed flat surface and the convex curved surface,

wherein the convex curved surface has a convex curvature in a first direction parallel to the top side of the semiconductor die and no curvature in a second direction parallel to the top side of the semiconductor die and intersecting the first direction.

2 . The molded package of claim 1 , wherein a bottom side of the substrate that faces away from the semiconductor die is not covered by the mold compound, such that the molded package has double-sided cooling via the top side of the electrically conductive clip and the bottom side of the substrate.

3 . The molded package of claim 2 , wherein the semiconductor die is a vertical power transistor die having a drain or collector terminal at the top side of the semiconductor die that is attached to the convex curved surface of the electrically conductive clip and a source or emitter terminal at the bottom side of the semiconductor die that is attached to the substrate.

4 . The molded package of claim 1 , wherein an edge of the electrically conductive clip that extends between the exposed flat surface and the convex curved surface has at least one feature that enhances locking between the mold compound and the electrically conductive clip.

5 . The molded package of claim 4 , wherein the at least one feature comprises at least one step covered by the mold compound.

6 . The molded package of claim 4 , wherein the at least one feature comprises at least one groove filled by the mold compound.

7 . The molded package of claim 4 , wherein the at least one feature comprises a curved surface covered by the mold compound.

8 . The molded package of claim 4 , wherein the at least one feature comprises a first step transition from the exposed flat surface and a second step transition from the convex curved surface, and wherein both the first step transition and the second step transition are covered by the mold compound.

9 . The molded package of claim 1 , wherein the substrate is a die paddle of a lead frame, wherein the electrically conductive clip is attached to one or more leads of the lead frame at an end of the electrically conductive clip opposite the semiconductor die, and wherein the mold compound partly encapsulates the one or more leads.

10 . The molded package of claim 1 , wherein the convex curved surface of the electrically conductive clip is attached to the top side of the semiconductor die by solder, and wherein a thickness of the solder is at a minimum at a vertex of the convex curved surface and increases outward from the vertex.

11 . The molded package of claim 1 , wherein the exposed flat surface has a larger area than the convex curved surface.

12 . The molded package of claim 1 , wherein one or more edges of the exposed flat surface extend beyond a corresponding edge of the convex curved surface.

13 . A molded package, comprising:

a semiconductor die;

a substrate attached to a bottom side of the semiconductor die;

an electrically conductive clip attached to a top side of the semiconductor die; and

a mold compound encapsulating the semiconductor die,

wherein a top side of the electrically conductive clip faces away from the semiconductor die and has a flat surface that overlays the semiconductor die and is not covered by the mold compound,

wherein a bottom side of the electrically conductive clip faces the semiconductor die and has a convex curved surface that is attached to the top side of the semiconductor die,

wherein the electrically conductive clip has a nonuniform thickness between the flat surface and the convex curved surface in a first direction parallel to the top side of the semiconductor die and a uniform thickness in a second direction parallel to the top side of the semiconductor die and intersecting the first direction,

wherein the nonuniform thickness is maximum at a vertex of the convex curved surface and decreases outward from the vertex.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2022
From: LEE, CHAI CHEE; GABRILLO, MARIE HAZEL BAROZZO; MOHAMED, NOR HAQIMI; LIM, WEE AUN JASON
To: INFINEON TECHNOLOGIES AG
Reel/Frame 062234/0904 →
Continuity (1)
Related Publication 20240087993A1 · Mar 14, 2024
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