IP Library Granted Patent US 12,745,663
Granted Patent B2
US 12,745,663 · App. 17/957,349 · Granted Sep 22, 2026

Singulation of integrated circuit package substrates with glass cores

Inventors: Whitney Bryks (Tempe, AZ); Kristof Darmawikarta (Chandler, AZ); Gang Duan (Chandler, AZ); Benjamin Duong (Phoenix, AZ); Srinivas Pietambaram (Chandler, AZ)
Assignee: Intel Corporation
H10W72/0198B23K26/364H10W70/05H10W70/095H10W70/65H10W70/685H10W70/692H10W74/012H10W74/15B23K2101/40B23K2103/54H10W74/014H10W74/016H10W90/724H10W90/794
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,745,663
App. No.
17/957,349
Granted
Sep 22, 2026
Kind
B2
Abstract

An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, and a sidewall between the first surface and the second surface. A build-up layer is on at least the first surface. A plurality of regions is on the sidewall. Each region comprises a cavity in the sidewall, wherein the cavity spans a first distance in a first direction from the first surface toward the second surface. In addition, the cavity comprises a concave surface having a first depth at the first surface and a second depth at the first distance, the second depth being less than the first depth.

Claims (47)

1 . An integrated circuit (IC) device comprising:

a substrate comprising a glass core, the glass core having a first surface, a second surface opposite the first surface, first, second, third, and fourth sidewalls between the first and second surfaces, the second sidewall opposite the first sidewall, the fourth sidewall opposite the third sidewall, wherein the first sidewall is spaced away from the second sidewall by a first distance, and the third sidewall is spaced away from the fourth sidewall by a second distance;

a build-up layer on at least the first surface; and

a plurality of regions on the first sidewall, each region comprising a cavity in the first sidewall, wherein the cavity:

spans a third distance in a first direction from the first surface toward the second surface;

spans a first depth at the first surface in a second direction from the first sidewall toward the second sidewall, the first depth being less than the first distance;

comprises a width at the first surface, the width being less than the second distance; and

comprises a concave cavity wall having a second depth at the third distance, the second depth being less than the first depth.

2 . The IC device of claim 1 , wherein the cavity wall comprises a scalloped surface away from the first surface.

3 . The IC device of claim 1 , wherein a first one of the plurality of regions is spaced apart from a second one of the plurality of regions.

4 . The IC device of claim 3 , wherein the first sidewall further comprises an artifact of a mechanical sawing process in a space between the first region and the second region.

5 . The IC device of claim 1 , wherein a first one of the plurality of regions at least partially overlaps with a second one of the plurality of regions.

6 . The IC device of claim 1 , wherein each region further comprises a second cavity in the first sidewall and the cavity wall is a first cavity wall, wherein the second cavity:

spans a fourth distance from the second surface in a third direction toward the first surface; and

comprises a concave second cavity wall having a third depth at the second surface and a fourth depth at the fourth distance, the fourth depth being less than the third depth.

7 . The IC device of claim 6 , wherein a fifth distance between the first surface and the second surface is a sum of the third distance and the fourth distance.

8 . The IC device of claim 1 , wherein the third distance is less than half of a fourth distance between the first surface and the second surface.

9 . The IC device of claim 1 , wherein the third distance is approximately equal to a fourth distance between the first surface and the second surface.

10 . The IC device of claim 1 , wherein the build-up layer comprises a metallization layer and a dielectric material layer.

11 . A system comprising:

an integrated circuit (IC) substrate comprising:

a glass core having a first surface, a second surface opposite the first surface, and a sidewall between the first surface and the second surface;

a build-up layer on at least the first surface;

a plurality of first regions on the sidewall, wherein each first region comprises a cavity in the sidewall, wherein the cavity spans a first distance in a first direction from the first surface toward the second surface; and

at least one second region on the sidewall that includes a chipped portion or a portion containing a crack, wherein the at least one second region is outside of the first regions.

12 . The system of claim 11 , wherein:

each cavity comprises a concave surface having a first depth at the first surface and a second depth at the first distance, the second depth being less than the first depth; and

each cavity comprises a cavity wall comprising a scalloped surface away from the first surface.

13 . The system of claim 11 , wherein:

the build-up layer comprises a metallization layer and a dielectric material layer; and

the system further comprises a power supply coupled with the build-up layer.

14 . A method comprising:

receiving a glass substrate comprising a first surface and a second surface opposite the first surface;

altering a microstructure of the glass substrate by treating a plurality of regions within singulation streets on the first surface with a laser, wherein a plurality of portions of the glass substrate are demarcated by the singulation streets;

forming a first perforation in each of the plurality of regions by removing glass substrate material using a wet etch process on the first surface; and

separating the glass substrate into the plurality of portions by performing mechanical sawing operations along lines coinciding with the plurality of regions.

15 . The method of claim 14 , further comprising:

forming a build-up layer on the first surface; and

removing the build-up layer from the singulation streets.

16 . The method of claim 14 , wherein the glass substrate comprises a build-up layer on at least the first surface, the method further comprising:

removing the build-up layer from the singulation streets.

17 . The method of claim 14 , wherein the first perforation comprises a depth extending from the first surface in a direction perpendicular to the first surface, the depth being substantially equal to one half of a distance between the first surface and the second surface.

18 . The method of claim 14 , wherein the first perforation comprises a depth extending from the first surface in a direction perpendicular to the first surface, and the depth is less than one half of a distance between the first surface and the second surface.

19 . The method of claim 14 , further comprising treating a plurality of regions within singulation streets on the second surface with a laser.

20 . The method of claim 19 , further comprising:

forming a second perforation in each of the plurality of regions using the wet etch process on the second surface, wherein each of the second perforations spans a first distance from the second surface in a direction toward the first surface; and

wherein the second perforations comprise a depth extending from the second surface in a direction perpendicular to the second surface, and the depth is substantially equal to one half of a second distance between the first surface and the second surface.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076008/0065 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2022
From: BRYKS, WHITNEY; DARMAWIKARTA, KRISTOF; DUAN, GANG; DUONG, BENJAMIN; PIETAMBARAM, SRINIVAS
To: INTEL CORPORATION
Reel/Frame 061273/0154 →
Continuity (1)
Related Publication 20240113072A1 · Apr 4, 2024
References Cited (27)
US 5199163A · Ehrenberg et al. · 1993 [cited by applicant]
US 6159757A · Kamimura · 2000 [cited by examiner]
US 7129114B2 · Akram · 2006 [cited by examiner]
US 7517423B2 · Furui · 2009 [cited by examiner]
US 7927916B2 · Lake · 2011 [cited by examiner]
US 8925192B2 · Noda · 2015 [cited by examiner]
US 10531577B1 · Grober · 2020 [cited by examiner]
US 10672718B2 · Sundaram · 2020 [cited by examiner]
US 11037904B2 · Yu · 2021 [cited by examiner]
US 11264279B2 · Xiao · 2022 [cited by examiner]
US 11380814B2 · Sommer · 2022 [cited by examiner]
US 11452212B2 · Tuominen · 2022 [cited by examiner]
US 12160955B2 · Kim · 2024 [cited by examiner]
US 20140238952A1 · Makino · 2014 [cited by examiner]
US 20150334823A1 · Hu · 2015 [cited by applicant]
US 20170023841A1 · N'Gom et al. · 2017 [cited by applicant]
US 20190019692A1 · Obata et al. · 2019 [cited by applicant]
US 20200364600A1 · Elsherbini et al. · 2020 [cited by applicant]
US 20230282546A1 · Waidhas et al. · 2023 [cited by applicant]
Ben-Yakar, A., et al., “Femtosecond laser ablation properties of borosilicate glass” , Journal of Applied Physics, vol. 96, No. 9, Nov. 1, 2004. [cited by applicant]
Bischof, D., et al., “Laser-assisted etching of borosilicate glass in potassium hydroxide” , Optical Materials Express, vol. 11, No. 4, Apr. 1, 2021. [cited by applicant]
Gray, S., et al., “Laser finished glass edges with compressive stress” , Optical Materials Express, vol. 10, No. 2, Feb. 1, 2020. [cited by applicant]
Hooper, A., et al., “Review of Wafer Dicing Techniques for Via-Middle Process 3DI/TSV Ultrathin Silicon Device Wafers” , Electronic Components & Technology Conference, 2015, 12 pages. [cited by applicant]
Liao, K., et al., “High quality full ablation cutting and stealth dicing of silica glass using picosecond laser Bessel beam with burst mode” , Ceramics International 48 (2022) 9805-9816. [cited by applicant]
Teng, A., “Comparison of Singulation Techniquest” IEEE Electronic Packaging Society, Silicon Valley Chapter, Sep. 28, 2017. [cited by applicant]
Iwatsuki, Soshi et al., “Examination of internal stress of photoelasticity in laser cleaving of glass,” Jul. 2020, Precision Engineering, vol. 63, pp. 122-128. [cited by applicant]
Kashyap, Raman et al., “Femtosecond-Induced Refractive Index Changes in Glass,” Nov. 30, 2009, Academic Press, Fiber Bragg Gratings Second Edition, pp. 503-525. [cited by applicant]