Semiconductor device and method of manufacturing the same
Provided is a semiconductor device. The semiconductor device includes a lower structure; a lower electrode on the lower structure; a dielectric layer on the lower electrode; and an upper electrode on the dielectric layer, wherein the lower electrode includes a bending reducing layer and a dielectric constant-increasing layer between the bending reducing layer and the dielectric layer, the dielectric constant-increasing layer is configured to increase a dielectric constant of the dielectric layer, and an elastic modulus of the bending reducing layer is greater than an elastic modulus of the dielectric constant-increasing layer.
1 . A semiconductor device comprising:
a lower structure;
a lower electrode on the lower structure;
an upper electrode; and
a dielectric layer between the lower electrode and the upper electrode,
wherein the lower electrode comprises a bending reducing layer and a dielectric constant-increasing layer between the bending reducing layer and the dielectric layer,
an upper surface of the bending reducing layer and an upper surface of the dielectric constant-increasing layer are substantially co-planar,
the dielectric constant-increasing layer is configured to increase a dielectric constant of the dielectric layer, and
an elastic modulus of the bending reducing layer is greater than an elastic modulus of the dielectric constant-increasing layer.
2 . The semiconductor device of claim 1 , wherein the bending reducing layer has a pillar shape.
3 . The semiconductor device of claim 2 , wherein the dielectric constant-increasing layer is on side surfaces of the bending reducing layer.
4 . The semiconductor device of claim 3 , wherein the dielectric constant-increasing layer extends between a bottom of the bending reducing layer and the lower structure.
5 . The semiconductor device of claim 1 , wherein the bending reducing layer comprises titanium (Ti), nitrogen (N), and X1, and
X1 is at least one element other than Ti and N.
6 . The semiconductor device of claim 5 , wherein X1 comprises at least one of silicon (Si), tungsten (W), carbon (C), or aluminum (Al).
7 . The semiconductor device of claim 1 , wherein the dielectric constant-increasing layer comprises X2 and X3,
X2 comprises at least one of molybdenum (Mo), tantalum (Ta), ruthenium (Ru), or niobium (Nb), and
X3 comprises at least one of nitrogen (N) or oxygen (O).
8 . The semiconductor device of claim 1 , wherein the dielectric layer comprises at least one of hafnium oxide or zirconium oxide.
9 . The semiconductor device of claim 1 , wherein the lower electrode further comprises a surface layer between the dielectric constant-increasing layer and the dielectric layer.
10 . The semiconductor device of claim 9 , wherein the surface layer comprises titanium nitride (TiN).
11 . A semiconductor device comprising:
a lower structure;
a lower electrode, comprising a surface layer on the lower structure, a bending reducing layer, and a dielectric constant-increasing layer between the surface layer and the bending reducing layer;
a support pattern contacting side surfaces of the lower electrode and supporting the lower electrode;
a dielectric layer on the lower electrode and the support pattern; and
an upper electrode on the dielectric layer,
wherein at least a portion of the dielectric constant-increasing layer is in direct contact with the dielectric layer, and
wherein an upper surface of the bending reducing layer and an upper surface of the dielectric constant-increasing layer are substantially co-planar.
12 . The semiconductor device of claim 11 , wherein the surface layer comprises titanium nitride (TiN), the dielectric constant-increasing layer comprises niobium nitride (NbN), and the bending reducing layer comprises titanium silicide nitride (TiSiN).
13 . The semiconductor device of claim 11 , wherein the surface layer comprises a side portion between the support pattern and the dielectric constant-increasing layer.
14 . The semiconductor device of claim 11 , wherein the surface layer comprises a bottom portion between the lower structure and a bottom of the dielectric constant-increasing layer.
15 . The semiconductor device of claim 11 , wherein the surface layer comprises a side portion between the lower structure and a side surface of the dielectric constant-increasing layer.
16 . A semiconductor device comprising:
a lower structure;
a lower electrode, comprising a surface layer on the lower structure, a bending reducing layer, and a dielectric constant-increasing layer between the surface layer and the bending reducing layer;
a support pattern contacting side surfaces of the lower electrode and supporting the lower electrode;
a dielectric layer on the lower electrode and the support pattern; and
an upper electrode on the dielectric layer,
wherein the bending reducing layer has a pillar shape extending in a vertical direction,
an upper surface of the bending reducing layer and an upper surface of the dielectric constant-increasing layer are substantially co-planar,
the surface layer comprises a first side portion in direct contact with the support pattern and a second side portion in direct contact with the dielectric layer, and
a thickness of the second side portion of the surface layer in a horizontal direction perpendicular to the vertical direction is less than a thickness of the first side portion of the surface layer.
17 . The semiconductor device of claim 16 , wherein the surface layer comprises a bottom portion between the lower structure and a bottom of the dielectric constant-increasing layer, and
the thickness of the second side portion of the surface layer in the horizontal direction is less than a thickness of the bottom portion of the surface layer in the vertical direction.
18 . The semiconductor device of claim 16 , wherein the surface layer comprises a third side portion between the lower structure and a side surface of the dielectric constant-increasing layer, and
the thickness of the second side portion of the surface layer in the horizontal direction is less than a thickness of the third side portion of the surface layer in the horizontal direction.
19 . The semiconductor device of claim 16 , wherein the dielectric constant-increasing layer is configured to increase a dielectric constant of the dielectric layer.
20 . The semiconductor device of claim 16 , wherein an elastic modulus of the bending reducing layer is greater than an elastic modulus of the surface layer and an elastic modulus of the dielectric constant-increasing layer.