IP Library › Granted Patent US 12,347,519

Granted Patent B2

US 12,347,519 · App. 17/966,350 · Granted Jul 1, 2025

Methods for reading data from a storage buffer including delaying activation of a column select

Inventor: Parthasarathy Gajapathy (Highland Village, TX)

Assignee: Micron Technology, Inc.

G11C7/12 G11C7/1018 G11C8/18 G11C11/4076

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 12,347,519
App. No.: 17/966,350
Granted: Jul 1, 2025
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.

Claims (163)

1. A state machine engine, comprising:

a bus interface configured to couple the state machine engine to a data bus;

a first finite state machine lattice comprising a first plurality of programmable hardware elements comprising a plurality of selectively couple-able hardware elements, wherein the first finite state machine lattice is configured to:

output a first state vector comprising a state of the first plurality of programmable hardware elements indicative of the match results between the first plurality of programmable hardware elements and the data to facilitate subsequent processing of the data; and

a first storage buffer coupled between the bus interface and the first finite state machine lattice, wherein the first storage buffer comprises a first portion of a memory cell array implemented in a memory device and the first storage buffer is configured to:

store the data received by the state machine engine in the first portion of the memory cell array; and

seamlessly supply the data to the first finite state machine lattice, wherein, to seamlessly supply the data, the first storage buffer is configured to:

select a first memory cell column in the first storage buffer to output a first portion of the data during a first array cycle;

select a second memory cell column in the first storage buffer to output a second portion of the data during a second array cycle; and

delay selection of a third memory cell column in the first storage buffer to delay output of a third portion of the data from the third memory cell column until at least a third array cycle that occurs two array cycles after the second array cycle to allow both the first portion of the data and the second portion of the data to be fully output from the first storage buffer prior to occurrence of the third array cycle, wherein selection of an occurrence of the third array cycle is determined based upon output operational characteristics of the first storage buffer related to output capacity of the first storage buffer.

2. The state machine engine of claim 1 , comprising a second finite state machine lattice, wherein the second finite state machine lattice comprises a second plurality of programmable hardware elements and the second finite state machine lattice is configured to:

analyze the data received by the state machine engine to generate second match results between the data and the second plurality of programmable hardware elements programmed with second processing criteria to implement a second finite state machine; and

output a second state vector indicative of the second match results between the second plurality of programmable hardware elements and the data received by the state machine engine to facilitate subsequent processing of the data;

wherein the first storage buffer is configured to seamlessly supply the data to the second finite state machine lattice in parallel with the first finite state machine lattice to facilitate analyzing the data based on the first processing criteria and the second processing criteria in parallel.

3. The state machine engine of claim 1 , comprising:

a second finite state machine lattice, wherein the second finite state machine lattice comprises a second plurality of programmable hardware elements and the second finite state machine lattice is configured to:

analyze input data to generate second match results between the data and the second plurality of programmable hardware elements programmed with second processing criteria to implement a second finite state machine; and

output a second state vector comprising a state of the second plurality of programmable hardware elements indicative of the second match results between the second plurality of programmable hardware elements and the input data to facilitate subsequent processing of the input data; and

a second storage buffer coupled between an output of the first finite state machine lattice and an input of the second finite state machine lattice, wherein the second storage buffer comprises a second portion of the memory cell array and the second storage buffer is configured to:

store the first state vector received from the first finite state machine lattice in the second portion of the memory cell array; and

seamlessly supply the first state vector to the second finite state machine lattice, wherein, to seamlessly supply the first state vector to the second finite state machine lattice, the second storage buffer is configured to:

select a first memory cell column in the second storage buffer to output a first portion of the first state vector during a fourth array cycle;

select a second memory cell column in the second storage buffer to output a second portion of the first state vector during a fifth array cycle; and

delay selection of a third memory cell column in the second storage buffer to output a third portion of the first state vector until at least a sixth array cycle that occurs two array cycles after the fifth array cycle.

4. The state machine engine of claim 1 , comprising a second storage buffer coupled between an output of the first finite state machine lattice and the bus interface, wherein the second storage buffer comprises a second portion of the memory cell array and the second storage buffer is configured to:

store the first state vector received from the first finite state machine lattice in the second portion of the memory cell array; and

seamlessly supply the first state vector to the bus interface, wherein, to seamlessly supply the first state vector to the bus interface, the second storage buffer is configured to:

select a first memory cell column in the second storage buffer to output a first portion of the first state vector during a fourth array cycle;

select a second memory cell column in the second storage buffer to output a second portion of the first state vector during a fifth array cycle; and

5. The state machine engine of claim 1 , wherein:

the each of the first plurality of programmable hardware elements is programmed to correspond with a state in the first finite state machine; and

the first finite state machine lattice comprises a plurality of programmable switching elements, wherein the plurality of programmable switching elements are programmed to correspond with transitions between states in the first finite state machine.

6. The state machine engine of claim 1 , wherein, to seamlessly supply the data to the first finite state machine lattice, the first storage buffer is configured to:

select the third memory cell column in the first storage buffer to output the third portion of the data during the third array cycle;

select a fourth memory cell column in the first storage buffer to output a fourth portion of the data during a fourth array cycle that occurs directly after the third array cycle; and

delay selection of a fifth memory cell column in the first storage buffer to output of a fifth portion of the data until at least a fifth array cycle that occurs two array cycles after the third array cycle.

7. The state machine engine of claim 1 , wherein, to seamlessly supply the data to the first finite state machine lattice, the first storage buffer is configured to:

select the third memory cell column in the first storage buffer to output the third portion of the data during the third array cycle that occurs two array cycles after the second array cycle when an input rate of the first storage buffer is two times an output rate of the first storage buffer; and

select the third memory cell column in the first storage buffer to output the third portion of the data during a fourth array cycle that occurs four array cycles after the second array cycle when the input rate of the first storage buffer is four times the output rate of the first storage buffer.

8. The state machine engine of claim 1 , comprising a plurality of registers coupled between the first storage buffer and data pins implemented on the memory device, wherein the plurality of registers is configured to:

receive and store the first portion of the data output from the first memory cell column in the first storage buffer while a column select signal is in a first state during the first array cycle;

output a first half of the first portion of the data from the plurality of registers to the data pins while the column select signal is in a second state during the first array cycle and while the column select signal is in the first state during the second array cycle;

receive and store the second portion of the data output from the second memory cell column in the first storage buffer while the column select signal is in the first state during the second array cycle;

output a second half of the first portion of the data from the plurality of registers to the data pins while the column select signal is in the second state during the second array cycle and during a fourth array cycle that occurs directly after the second array cycle;

output a first half of the second portion of the data from the plurality of registers to the data pins during the fourth array cycle and a fifth array cycle that occurs directly before the third array cycle; and

output a second half of the second portion of the data from the plurality of registers to the data pins during fifth array cycle and while the column select signal is in the first state during the third array cycle.

9. The state machine engine of claim 1 , wherein the first storage buffer does not include any registers.

10. The state machine engine of claim 1 , comprising a second storage buffer communicatively coupled to an output of the first finite state machine lattice, wherein:

the second storage buffer comprises a second portion of the memory cell array;

the second storage buffer comprises a state vector memory buffer, a state vector immediate output buffer, a match buffer, or any combination thereof; and

the first storage buffer comprises a data buffer, a process buffer, a state vector intermediate input buffer, or any combination thereof.

11. The state machine engine of claim 1 , wherein the bus interface comprises a double data rate interface, a peripheral component interconnect interface, a NAND interface, or a flash interface.

12. The state machine engine of claim 1 , wherein the memory device comprises dynamic random access memory, static random access memory, cross-point memory, or any combination thereof.

13. A state machine engine, comprising:

a bus interface configured to couple the state machine engine to a data bus;

analyze data received by the state machine engine to generate match results between the data and the first plurality of programmable hardware elements programmed with first processing criteria to implement a first finite state machine, wherein the data received by the state machine engine comprises a data stream received over a communication network and wherein the first finite state machine lattice is configured to analyze the data received by the state machine engine to facilitate detecting presence of spam, malware, or both in the data stream; and

store the data received by the state machine engine in the first portion of the memory cell array; and

seamlessly supply the data to the first finite state machine lattice, wherein, to seamlessly supply the data, the first storage buffer is configured to:

select a first memory cell column in the first storage buffer to output a first portion of the data during a first array cycle;

select a second memory cell column in the first storage buffer to output a second portion of the data during a second array cycle; and

14. A method for operating a storage buffer implemented in a state machine engine, comprising:

instructing, using at least one processor, a finite state machine lattice comprising a plurality of programmable hardware elements comprising a plurality of selectively couple-able hardware elements to program one or more of the plurality of programmable hardware elements with first processing criteria to implement a finite state machine in the state machine engine;

instructing, using the at least one processor, a first storage buffer comprising a first portion of a memory array implemented in a memory device to store data received by the state machine engine; and

instructing, using the at least one processor, the first storage buffer to supply the data received by the state machine engine to the finite state machine lattice to enable the finite state machine lattice to analyze the data to generate match results between the data and the plurality of programmable hardware elements programmed with the first processing criteria to implement the finite state machine and to determine and output a state vector comprising a state of the plurality of programmable hardware elements indicative of the match results between the plurality of programmable hardware elements and the data to facilitate subsequent processing of the data, wherein supplying the data received by the state machine engine to the finite state machine lattice comprises:

activating a first memory cell column in the first portion of the memory array included in the first storage buffer to output a first portion of the data from the first memory cell column during a first array cycle;

activating a second memory cell column in the first portion of the memory array included in the first storage buffer to output a second portion of the data from the second memory cell column during a second array cycle; and

abstaining from activation of a third memory cell column in the first portion of the memory array included in the first storage buffer to delay output of a third portion of the data from the third memory cell column until a third array cycle that occurs at least two array cycles after the second array cycle to allow both the first portion of the data and the second portion of the data to be fully output from the first storage buffer prior to occurrence of the third array cycle, wherein selection of an occurrence of the third array cycle is determined based upon output operational characteristics of the first storage buffer related to output capacity of the first storage buffer.

15. The method of claim 14 , comprising:

instructing, using the at least one processor, a second storage buffer comprising a second portion of the memory array to store the state vector output from the finite state machine lattice; and

instructing, using the at least one processor, the second storage buffer to output the state vector to a data bus coupled to the state machine engine, wherein outputting the state vector to the data bus comprises:

activating a first memory cell column in the second portion of the memory array included in the second storage buffer to output a first portion of the state vector from the first memory cell column during a fourth array cycle;

activating a second memory cell column in the second portion of the memory array included in the second storage buffer to output a second portion of the state vector from the second memory cell column during a fifth array cycle; and

abstaining from activation of a third memory cell column in the second portion of the memory array included in the second storage buffer to delay output of a third portion of the state vector from the third memory cell column in the second portion of the memory array until a sixth array cycle that occurs at least two array cycles after the fifth array cycle.

16. The method of claim 14 , wherein supplying the data received by the state machine engine to the finite state machine lattice comprises:

receiving and storing the first portion of the data output from the first memory cell column in the first storage buffer in a plurality of registers while a column select signal is in a high state during the first array cycle;

outputting a first half of the first portion of the data from the plurality of registers to data pins formed on memory device while the column select signal is in a low state during the first array cycle and while the column select signal is in the high state during the second array cycle;

receiving and storing the second portion of the data output from the second memory cell column in the first storage buffer in the plurality of registers while the column select signal is in the high state during the second array cycle;

outputting a second half of the first portion of the data from the plurality of registers to the data pins while the column select signal is in the low state during the second array cycle and during a fourth array cycle that occurs directly after the second array cycle;

outputting a first half of the second portion of the data from the first storage buffer to the data pins during the fourth array cycle and a fifth array cycle that occurs directly before the third array cycle; and

outputting a second half of the second portion of the data from the first storage buffer to the data pins during fifth array cycle and while the column select signal is in the high state during the third array cycle.

17. The method of claim 14 , wherein supplying the data received by the state machine engine to the finite state machine lattice comprises:

activating the third memory cell column in the first portion of the memory array included in the first storage buffer to output the third portion of the data from the third memory cell column during the third array cycle;

activating a fourth memory cell column in the first portion of the memory array included in the first storage buffer to output a fourth portion of the data from the fourth memory cell column during a fourth array cycle; and

abstaining from activation of a fifth memory cell column in the first portion of the memory array included in the first storage buffer to delay output of a fifth portion of the data from the fifth memory cell column until a fifth array cycle that occurs at least two array cycles after the second array cycle.

18. A method for operating a storage buffer implemented in a state machine engine, comprising:

instructing, using at least one processor, a finite state machine lattice comprising a plurality of programmable hardware elements comprising a plurality of selectively couple-able hardware elements that correspond to a plurality of states of a finite state machine in the state machine engine to program one or more of the plurality of programmable hardware elements with first processing criteria to implement the finite state machine in the state machine engine;

instructing, using the at least one processor, the first storage buffer to supply the data received by the state machine engine to the finite state machine lattice to enable the finite state machine lattice to analyze the data to generate match results between the data and the plurality of programmable hardware elements programmed with the first processing criteria to implement the finite state machine and to determine and output a state vector comprising a state of the plurality of programmable hardware elements indicative of the match results between the plurality of programmable hardware elements and the data to facilitate subsequent processing of the data, wherein a presence of spam, malware, or both is detected in the data analyzed by the finite state machine lattice based at least in part on the state vector determined by the finite state machine lattice, wherein the data analyzed by the state machine engine comprises a data stream received over a communication network, wherein supplying the data received by the state machine engine to the finite state machine lattice comprises:

19. A system comprising a memory module, wherein the memory module comprises:

data pins configured to communicatively couple the memory module to an external data bus;

an array of memory cells each configured to store data;

a first storage buffer comprising a first portion of the array; and

a memory controller configured to operate the memory cells implemented in the first portion of the array by instructing the array to:

store input data to be analyzed by the system in the memory cells implemented in the first portion of the array;

activate a first column in the first portion of the array to output a first portion of the input data from the first column in the first portion of the array during a first array cycle via transitioning a column select signal in response to a first pulse of a read command signal;

activate a second column in the first portion of the array to output a second portion of the input data from the second column in the first portion of the array during a second array cycle directly after the first array cycle via transitioning the column select signal in response to a second pulse of the read command signal directly subsequent to the first pulse of the read command signal;

delay activation of a third column in the first portion of the array by abstaining from transitioning a column select signal in response to a third pulse of a read command signal directly subsequent to the second pulse of the read command signal for a predetermined number of cycle array times beyond the second array cycle to delay output of a third portion of the input data from the third column in the first portion of the array; and

complete a transfer of the first portion of the input data and the second portion of the input data during the predetermined number of cycle array times beyond the second array cycle to allow both the first portion of the input data and the second portion of the input data to be fully output from the first storage buffer during the predetermined number of cycle array times, wherein selection of the predetermined number of cycle array times is determined based upon output operational characteristics of the first storage buffer related to output capacity of the first storage buffer.

20. A system, comprising:

a memory module, wherein the memory module comprises:

data pins configured to communicatively couple the memory module to an external data bus;

an array of memory cells each configured to store data;

a first storage buffer comprising a first portion of the array; and

a memory controller configured to operate the memory cells implemented in the first portion of the array by instructing the array to:

store input data to be analyzed by the system in the memory cells implemented in the first portion of the array;

complete a transfer of the first portion of the input data and the second portion of the input data during the predetermined number of cycle array times beyond the second array cycle;

a communication port configured to communicatively couple the system to a communication network that transmits a data stream comprising the input data to be analyzed by the system;

a hardware element coupled between the first storage buffer and the external data bus, wherein the hardware element is programmed to implement at least a portion of a finite state machine that outputs a state vector based at least in part on analysis of the input data; and

a processor coupled to the external data bus, wherein the processor is programmed to detect presence of spam, malware, or both in the data stream based at least in part on the state vector.

21. The system of claim 19 , wherein, to operate the memory cells implemented in the first portion of the array as the first storage buffer, the memory controller is configured to:

abstain from activation of the third column in the first portion of the array to preclude output of the third portion of the input data from the third column in the first portion of the array during a fourth array cycle that occurs directly after the second array cycle;

abstain from activation of the third column in the first portion of the array to preclude output of the third portion of the input data from the third column in the first portion of the array during a fifth array cycle that occurs directly after the fourth array cycle; and

activate the third column in the first portion of the array to output the third portion of the input data from the third column in the first portion of the array during a third array cycle that occurs directly after the fifth array cycle.

22. The system of claim 19 , comprising a hardware element coupled between the first storage buffer and the external data bus, wherein:

the hardware element is programmed to implement at least a portion of a finite state machine that outputs a state vector based at least in part on analysis of the input data; and

the memory controller configured to operate the memory cells implemented in a second portion of the array as a second storage buffer by instructing the array to:

store the state vector output from the finite state machine in the memory cells implemented in the second portion of the array;

activate a first column in the second portion of the array to output a first portion state vector from the first column in the second portion of the array during a fourth array cycle;

activate a second column in the second portion of the array to output a second portion of the state vector from the second column in the second portion of the array during a fifth array cycle directly after the fourth array cycle; and

delay activation of a third column in the second portion of the array to delay output of a third portion of the state vector from the third column in the second portion of the array until a sixth array cycle that occurs two array cycles after the fifth array cycle.

23. The system of claim 19 , wherein, to operate the memory cells implemented in the first portion of the array as the first storage buffer, the memory controller configured to:

activate the third column in the first portion of the array to output the third portion of the input data from the first column in the first portion of the array during a third array cycle directly after the predetermined number of cycle array times;

activate a fourth column in the first portion of the array to output a fourth portion of the input data from the fourth column in the first portion of the array during a fourth array cycle directly after the third array cycle; and

delay activation of a fifth column in the first portion of the array to delay output of a fifth portion of the input data from the fifth column in the first portion of the array until a fifth array cycle that occurs two array cycles after the second array cycle.

24. The system of claim 19 , wherein the memory controller configured to operate the memory cells implemented in a second portion of the array as system memory.

25. The system of claim 19 , wherein the first storage buffer does not include any registers.

26. The system of claim 19 , wherein:

the first storage buffer comprises a word line coupled to a row of memory cells in the array of memory cells;

the first column in the first portion of the array comprises a first plurality of bit lines each coupled to a column of memory cells in the first portion of the array;

the second column in the first portion of the array comprises a second plurality of bit lines each coupled to a column of memory cells in the first portion of the array; and

the third column in the first portion of the array comprises a third plurality of bit lines each coupled to a column of memory cells in the first portion of the array.

27. The system of claim 19 , comprising a hardware element communicatively coupled to the first storage buffer, wherein the hardware element is programmed with processing criteria such that the hardware element selectively activates a downstream hardware element based at least in part on a match between the input data and the processing criteria to facilitate analyzing the input data.

28. A storage buffer comprising:

a word line coupled to a row of memory cells implemented in a memory cell array, wherein the row of memory cells is configured to store data to be output from the storage buffer;

a first column comprising a first plurality of bit lines each coupled to one of a first plurality of memory cells in the row of memory cells;

a second column comprising a second plurality of bit lines each coupled to one of a second plurality of memory cells in the row of memory cells; and

a third column comprising a third plurality of bit lines each coupled to one of a third plurality of memory cells in the row of memory cells;

wherein, in response to receipt of a read command, the storage buffer is configured to:

pulse a column select signal in response to a first pulse of a read command signal during a first array cycle to activate the first column such that each of the first plurality of memory cells outputs one bit of the data as first output data to a corresponding one of the first plurality of bit lines;

pulse the column select signal in response to a second pulse of the read command signal directly subsequent to the first pulse of the read command signal during a second array cycle directly after the first array cycle to activate the second column such that each of the second plurality of memory cells outputs one bit of the data as second output data to a corresponding one of the second plurality of bit lines;

abstain from pulsing of the column select signal in response to a plurality of pulses of the read command signal directly subsequent to the second pulse of the read command signal during a first plurality of array cycles that occur directly after the second array cycle;

complete a transfer of the first output data and the second output data during the first plurality of array cycles that occur directly after the second array cycle to allow both the first output data and the second output data to be fully output from the storage buffer during the first plurality of array cycles, wherein selection of the first plurality of array cycles is determined based upon output operational characteristics of the storage buffer related to output capacity of the storage buffer; and

pulse the column select signal during a third array cycle directly after the first plurality of array cycles to activate the third column such that each of the third plurality of memory cells outputs one bit of the data as third output data to the corresponding one of the third plurality of bit lines.

29. The storage buffer of claim 28 , comprising a fourth column, wherein:

the fourth column comprises a fourth plurality of bit lines each coupled to one of a fourth plurality of memory cells in the row of memory cells; and

the storage buffer is configured to pulse the column select signal during a fourth array cycle directly after the third array cycle to activate the fourth column such that each of the fourth plurality of memory cells outputs one bit of the data to a corresponding one of the fourth plurality of bit lines in response to receipt of the read command.

30. The storage buffer of claim 29 , comprising a fifth column, wherein:

the fifth column comprises a fifth plurality of bit lines each coupled to one of a fifth plurality of memory cells in the row of memory cells; and

in response to receipt of the read command, the storage buffer is configured to:

abstain from pulsing of the column select signal during a second plurality of array cycles that occur directly after the fourth array cycle; and

pulse the column select signal during a fifth array cycle directly after the second plurality of array cycles to activate the fifth column such that each of the fifth plurality of memory cells outputs one bit of the data to a corresponding one of the fifth plurality of bit lines.

Continuity (3)

Continuation 15965263 · Apr 27, 2018

Continuation 13445659 · Apr 12, 2012

Related Publication 20230039948A1 · Feb 9, 2023

References Cited (229)

US 3849762A · Fujimoto et al. · 1974 [cited by applicant]

US 3921136A · Bar-Lev · 1975 [cited by applicant]

US 4011547A · Kimmel · 1977 [cited by applicant]

US 4014000A · Uno et al. · 1977 [cited by applicant]

US 4123695A · Hale et al. · 1978 [cited by applicant]

US 4153897A · Yasuda et al. · 1979 [cited by applicant]

US 4204193A · Schroeder · 1980 [cited by applicant]

US 4414685A · Sternberg · 1983 [cited by applicant]

US 4748674A · Freeman · 1988 [cited by applicant]

US 5014327A · Potter et al. · 1991 [cited by applicant]

US 5028821A · Kaplinsky · 1991 [cited by applicant]

US 5216748A · Quenot et al. · 1993 [cited by applicant]

US 5257361A · Doi et al. · 1993 [cited by applicant]

US 5287523A · Allison et al. · 1994 [cited by applicant]

US 5291482A · McHarg et al. · 1994 [cited by applicant]

US 5300830A · Hawes · 1994 [cited by applicant]

US 5331227A · Hawes · 1994 [cited by applicant]

US 5357512A · Khaira et al. · 1994 [cited by applicant]

US 5371878A · Coker · 1994 [cited by applicant]

US 5377129A · Molvig et al. · 1994 [cited by applicant]

US 5459798A · Bailey et al. · 1995 [cited by applicant]

US 5615237A · Chang et al. · 1997 [cited by applicant]

US 5659551A · Huott et al. · 1997 [cited by applicant]

US 5723984A · Sharpe-Geisier · 1998 [cited by applicant]

US 5754878A · Asghar et al. · 1998 [cited by applicant]

US 5790531A · Ellebracht et al. · 1998 [cited by applicant]

US 5881312A · Dulong · 1999 [cited by applicant]

US 5896548A · Ofek · 1999 [cited by applicant]

US 5956741A · Jones · 1999 [cited by applicant]

US 6011407A · New · 2000 [cited by applicant]

US 6016361A · Hongu et al. · 2000 [cited by applicant]

US 6034918A · Farmwald · 2000 [cited by examiner]

US 6034963A · Minami et al. · 2000 [cited by applicant]

US 6041405A · Green · 2000 [cited by applicant]

US 6052766A · Betker et al. · 2000 [cited by applicant]

US 6058469A · Baxter · 2000 [cited by applicant]

US 6094711A · Wong · 2000 [cited by examiner]

US 6151644A · Wu · 2000 [cited by applicant]

US 6240003B1 · McElroy · 2001 [cited by applicant]

US 6279128B1 · Arnold et al. · 2001 [cited by applicant]

US 6317427B1 · Augusta et al. · 2001 [cited by applicant]

US 6321315B1 · LaBerge · 2001 [cited by examiner]

US 6338137B1 · Shiell · 2002 [cited by examiner]

US 6362868B1 · Silverbrook · 2002 [cited by applicant]

US 6400996B1 · Hoffberg et al. · 2002 [cited by applicant]

US 6606699B2 · Pechanek et al. · 2003 [cited by applicant]

US 6614703B2 · Pitts et al. · 2003 [cited by applicant]

US 6625740B1 · Datar et al. · 2003 [cited by applicant]

US 6633443B1 · Watanabe et al. · 2003 [cited by applicant]

US 6636483B1 · Pannell · 2003 [cited by applicant]

US 6640262B1 · Uppunda et al. · 2003 [cited by applicant]

US 6665209B2 · Osada et al. · 2003 [cited by applicant]

US 6697979B1 · Vorbach et al. · 2004 [cited by applicant]

US 6700404B1 · Feng et al. · 2004 [cited by applicant]

US 6880087B1 · Carter · 2005 [cited by applicant]

US 6906938B2 · Kaginele · 2005 [cited by applicant]

US 6928494B1 · Volk · 2005 [cited by examiner]

US 6944710B2 · Regev et al. · 2005 [cited by applicant]

US 6977897B1 · Nelson et al. · 2005 [cited by applicant]

US 7010639B2 · Larson et al. · 2006 [cited by applicant]

US 7089352B2 · Regev et al. · 2006 [cited by applicant]

US 7146643B2 · Dapp et al. · 2006 [cited by applicant]

US 7176717B2 · Sunkavalli et al. · 2007 [cited by applicant]

US 7276934B1 · Young · 2007 [cited by applicant]

US 7305047B1 · Turner · 2007 [cited by applicant]

US 7358761B1 · Sunkavalli et al. · 2008 [cited by applicant]

US 7366352B2 · Kravec et al. · 2008 [cited by applicant]

US 7392229B2 · Harris et al. · 2008 [cited by applicant]

US 7428722B2 · Sunkavalli et al. · 2008 [cited by applicant]

US 7487131B2 · Harris et al. · 2009 [cited by applicant]

US 7487542B2 · Boulanger et al. · 2009 [cited by applicant]

US 7499464B2 · Ayrapetian et al. · 2009 [cited by applicant]

US 7774286B1 · Harris · 2010 [cited by applicant]

US 7804719B1 · Chirania et al. · 2010 [cited by applicant]

US 7890923B2 · Elaasar · 2011 [cited by applicant]

US 7899052B1 · Hao et al. · 2011 [cited by applicant]

US 7917684B2 · Noyes et al. · 2011 [cited by applicant]

US 7970964B2 · Noyes · 2011 [cited by applicant]

US 8015530B1 · Sinclair et al. · 2011 [cited by applicant]

US 8020131B1 · Van Mau et al. · 2011 [cited by applicant]

US 8065249B1 · Harris et al. · 2011 [cited by applicant]

US 8140780B2 · Noyes · 2012 [cited by applicant]

US 8146040B1 · Janneck et al. · 2012 [cited by applicant]

US 8159900B2 · Moore et al. · 2012 [cited by applicant]

US 8209521B2 · Noyes et al. · 2012 [cited by applicant]

US 8239660B2 · Cervini · 2012 [cited by applicant]

US 8281395B2 · Pawlowski · 2012 [cited by applicant]

US 8294490B1 · Kaviani · 2012 [cited by applicant]

US 8402188B2 · Noyes et al. · 2013 [cited by applicant]

US 8536896B1 · Trimberger · 2013 [cited by applicant]

US 8593175B2 · Noyes et al. · 2013 [cited by applicant]

US 8648621B2 · Noyes et al. · 2014 [cited by applicant]

US 8680888B2 · Brown et al. · 2014 [cited by applicant]

US 8725961B2 · Noyes · 2014 [cited by applicant]

US 8782624B2 · Brown et al. · 2014 [cited by applicant]

US 8938590B2 · Noyes et al. · 2015 [cited by applicant]

US 9058465B2 · Noyes et al. · 2015 [cited by applicant]

US 9063532B2 · Brown · 2015 [cited by applicant]

US 9075428B2 · Brown · 2015 [cited by applicant]

US 9118327B2 · Noyes et al. · 2015 [cited by applicant]

US 9235798B2 · Brown et al. · 2016 [cited by applicant]

US 20020186044A1 · Agrawal et al. · 2002 [cited by applicant]

US 20030107996A1 · Black et al. · 2003 [cited by applicant]

US 20030142698A1 · Parhl · 2003 [cited by applicant]

US 20030163615A1 · Yu · 2003 [cited by applicant]

US 20030226002A1 · Boutaud et al. · 2003 [cited by applicant]

US 20040100980A1 · Jacobs et al. · 2004 [cited by applicant]

US 20040125807A1 · Liu et al. · 2004 [cited by applicant]

US 20040151211A1 · Snider · 2004 [cited by applicant]

US 20040184662A1 · Kravec et al. · 2004 [cited by applicant]

US 20050154916A1 · Boulanger et al. · 2005 [cited by applicant]

US 20050251638A1 · Boutaud et al. · 2005 [cited by applicant]

US 20060158219A1 · Sunkavalli et al. · 2006 [cited by applicant]

US 20060195496A1 · Vadi et al. · 2006 [cited by applicant]

US 20060206875A1 · Ullmann et al. · 2006 [cited by applicant]

US 20060257043A1 · Chiu · 2006 [cited by applicant]

US 20060274001A1 · Guttag et al. · 2006 [cited by applicant]

US 20060288070A1 · Vadi et al. · 2006 [cited by applicant]

US 20070005869A1 · Balraj et al. · 2007 [cited by applicant]

US 20070075878A1 · Furodet et al. · 2007 [cited by applicant]

US 20070127482A1 · Harris et al. · 2007 [cited by applicant]

US 20070150623A1 · Kravec et al. · 2007 [cited by applicant]

US 20070282833A1 · McMillen · 2007 [cited by applicant]

US 20070283108A1 · Isherwood et al. · 2007 [cited by applicant]

US 20080126690A1 · Rajan et al. · 2008 [cited by applicant]

US 20080129334A1 · Sunkavalli et al. · 2008 [cited by applicant]

US 20080133874A1 · Capek et al. · 2008 [cited by applicant]

US 20080140661A1 · Pandya · 2008 [cited by applicant]

US 20080178031A1 · Dong-Han · 2008 [cited by applicant]

US 20080256347A1 · Eickemeyer et al. · 2008 [cited by applicant]

US 20080320053A1 · Iijima et al. · 2008 [cited by applicant]

US 20090198952A1 · Khmelnitsky et al. · 2009 [cited by applicant]

US 20090204734A1 · Strait et al. · 2009 [cited by applicant]

US 20100100691A1 · Noyes et al. · 2010 [cited by applicant]

US 20100100714A1 · Noyes et al. · 2010 [cited by applicant]

US 20100115173A1 · Noyes · 2010 [cited by applicant]

US 20100115347A1 · Noyes · 2010 [cited by applicant]

US 20100118425A1 · Rafaelof · 2010 [cited by applicant]

US 20100138432A1 · Noyes · 2010 [cited by applicant]

US 20100138575A1 · Noyes · 2010 [cited by applicant]

US 20100138634A1 · Noyes · 2010 [cited by applicant]

US 20100138635A1 · Noyes · 2010 [cited by applicant]

US 20100175130A1 · Pawlowski · 2010 [cited by applicant]

US 20100174887A1 · Pawlowski · 2010 [cited by applicant]

US 20100174929A1 · Pawlowski · 2010 [cited by applicant]

US 20100185647A1 · Noyes · 2010 [cited by applicant]

US 20100145182A1 · Schmidt et al. · 2010 [cited by applicant]

US 20100325352A1 · Schuette et al. · 2010 [cited by applicant]

US 20100332809A1 · Noyes et al. · 2010 [cited by applicant]

US 20110004578A1 · Momma et al. · 2011 [cited by applicant]

US 20110145182A1 · Dlugosch · 2011 [cited by applicant]

US 20110145544A1 · Noyes et al. · 2011 [cited by applicant]

US 20110161620A1 · Kaminski et al. · 2011 [cited by applicant]

US 20110208900A1 · Schuette et al. · 2011 [cited by applicant]

US 20110258360A1 · Noyes · 2011 [cited by applicant]

US 20110145271A1 · Noyes et al. · 2011 [cited by applicant]

US 20110307233A1 · Tseng et al. · 2011 [cited by applicant]

US 20110307433A1 · Dlugosch · 2011 [cited by applicant]

US 20110307503A1 · Dlugosch · 2011 [cited by applicant]

US 20110320759A1 · Craddock et al. · 2011 [cited by applicant]

US 20120192163A1 · Glendenning et al. · 2012 [cited by applicant]

US 20120179854A1 · Noyes · 2012 [cited by applicant]

US 20120192164A1 · Xu et al. · 2012 [cited by applicant]

US 20120192165A1 · Xu et al. · 2012 [cited by applicant]

US 20120192166A1 · Xu et al. · 2012 [cited by applicant]

US 20130156043A1 · Brown et al. · 2013 [cited by applicant]

US 20130159239A1 · Brown et al. · 2013 [cited by applicant]

EP 0476159A1 · 1992 [cited by applicant]

EP 0943995 · 1999 [cited by applicant]

JP 08087462 · 1996 [cited by applicant]

JP 10069459 · 1998 [cited by applicant]

JP 10111862A · 1998 [cited by applicant]

JP 2000231549A · 2000 [cited by applicant]

JP 2000347708A · 2000 [cited by applicant]

KR 1020080097573A · 2008 [cited by applicant]

WO WO0065425A1 · 2000 [cited by applicant]

WO WO0138978 · 2001 [cited by applicant]

WO WO03039001A1 · 2003 [cited by applicant]

WO WO2005036750A1 · 2005 [cited by applicant]

WO WO2011114120A1 · 2011 [cited by applicant]

Beesley, K. R.; Arabic Morphology Using Only Finite-State Operations; Xerox Research Centre Europe; pp. 50-57; 1998. [cited by applicant]

Bird, S. et al.; One-Level Phonology: Autosegmental Representations and Rules as Finite Automata; Association for Computational Linguistics; University of Edinburgh; vol. 20; No. 1; pp. 55-90; 1994. [cited by applicant]

Bispo, J. et al.; Regular Expression Matching for Reconfigurable Packet Inspection; IEEE; 2006. [cited by applicant]

Bispo, J. et al.; Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues; IST/INESC-ID, Libson, Portugal; pp. 1-12; 2007. [cited by applicant]

Brodie, B. et al.; A scalable Architecture for High-Throughput Regular-Expression Pattern Matching; Exegy Inc.; pp. 1-12; 2006. [cited by applicant]

Clark, C.; Design of Efficient FPGA Circuits for Matching Complex Patterns in Network Intrusion Detection Systems (Master of Science Thesis); Georgia Institute of Technology; pp. 1-56; Dec. 2003. [cited by applicant]

Clark, C.; A Unified Model of Pattern-Matching Circuits for Field-Programmable Gate Arrays [Doctoral Dissertation]; Georgia Institute of Technology; pp. 1-177; 2006. [cited by applicant]

Clark, C. et al.; Scalable Pattern Matching for High Speed Networks; Proceedings of the 12 [cited by applicant]

Clark, C. et al.; A Unified Model of Pattern-Matching Circuit Architectures; Tech Report GIT-CERCS-05-20;Georgia Institute of Technology; pp. 1-17; 2005. [cited by applicant]

Fide, S.; String Processing in Hardware; Scalable Parallel and Distributed Systems Lab; Proceedings of the 12 [cited by applicant]

Fisk, M. et al.; Applying Fast String Matching to Intrusion Detection; Los Alamos National Laboratory; University of California San Diego; pp. 1-21; 2002. [cited by applicant]

Korenek, J.; Traffic Scanner-Hardware Accelerated Intrusion Detection System; http://www.liberouter.org/; 2006. [cited by applicant]

Kumar, S. et al.; Curing Regular Expressions matching Algorithms from Insomnia, Amnesia, and Acaluia; Department of Computer Science and Engineering; Washington University in St. Louis; pp. 1-17; Apr. 27, 2007. [cited by applicant]

Lipovski, G.; Dynamic Systolic Associative Memory Chip; IEEE; Department of Electrical and Computer Engineering; University of Texas at Austin; pp. 481-492; 1990. [cited by applicant]

Lin, C. et al.; Optimization of Pattern Matching Circuits for Regular Expression on FPGA; IEEE Transactions on Very Large Scale Integrations Systems; vol. 15, No. 12, pp. 1-6; Dec. 2007. [cited by applicant]

Schultz, K. et al.; Fully Parallel Integrated CAM/RAM Using Preclassification to Enable Large Capacities; IEEE Journal on Solid-State Circuits; vol. 31; No. 5; pp. 689-699; May 1996. [cited by applicant]

Shafai, F. et al.; Fully Parallel 30-MHz, 2.5-Mb CAM; IEEE Journal of Solid-State Circuits, vol. 33; No. 11; pp. 1690-1696; Nov. 1998. [cited by applicant]

Sidhu, R. et al.; Fast Regular Expression Pattern Matching using FPGAs; Department of EE-Systems; University of Southern California; pp. 1-12; 2001. [cited by applicant]

Wada, T.; Multiobject Behavior Recognition Event Driven Selective Attention Method; IEEE; pp. 1-16; 2000. [cited by applicant]

Yu, F.; High Speed Deep Packet Inspection with Hardware Support; Electrical Engineering and Computer Sciences; University of California at Berkeley; pp. 1-217; Nov. 22, 2006. [cited by applicant]

Freescale and Kaspersky® Accelerated Antivirus Solution Platform for OEM Vendors; Freescale Semiconductors Document; pp. 1-16; 2007. [cited by applicant]

PCT/US2009/067534 International Search Report and Written Opinion Apr. 26, 2010. [cited by applicant]

PCT/US2009/061649 International Search Report Feb. 15, 2012. [cited by applicant]

Taiwan Application No. 098144804 Office Action dated Feb. 4, 2013. [cited by applicant]

PCT/US2012/067992 International Search Report Mar. 28, 2013. [cited by applicant]

PCT/US2012/068011 International Search Report Apr. 15, 2013. [cited by applicant]

PCT/US2012/067999 International Search Report May 14, 2013. [cited by applicant]

PCT/US2012/067995 International Search Report May 17, 2013. [cited by applicant]

PCT/US2012/067988 International Search Report (Partial) Jun. 24, 2014. [cited by applicant]

PCT/US2013/049744 International Search Report and Written Opinion Oct. 22, 2013. [cited by applicant]

PCT/US2013/049748 International Search Report and Written Opinion Oct. 22, 2013. [cited by applicant]

PCT/US2013/049755 International Search Report and Written Opinion Oct. 24, 2013. [cited by applicant]

PCT/US2013/049753 International Search Report and Written Opinion Nov. 7, 2013. [cited by applicant]

PCT/US2013/055434 International Search Report and Written Opinion Nov. 11, 2013. [cited by applicant]

PCT/US2013/055438 International Search Report and Written Opinion Nov. 29, 2013. [cited by applicant]

PCT/US2013/055436 International Search Report and Written Opinion Dec. 9, 2013. [cited by applicant]

PCT/US2014/023589 International Search Report and Written Opinion Jul. 24, 2014. [cited by applicant]

Soewito et al., “Self-Addressable Memory-Based FSM: A scalable Intrusion Detection Engine”, IEEE Network, pp. 14-2, Feb. 2009. [cited by applicant]

Hurson A. R.; A VLSI Design for the Parallel Finite State Automation and Its Performance Evaluation as a Hardware Scanner; International Journal of Computer and Information Sciences, vol. 13, No. 6; 1984. [cited by applicant]

Carpenter et al., “A Massively Parallel Architecture for a Self-Organizing Neural Pattern Recognition Machine”, Academic Press, Inc.; 1987. [cited by applicant]

Cong et al., “Application-Specific Instruction Generation for Configurable Processor Architectures”, Computer Science Department, University of California, ACM 2004. [cited by applicant]

Glette et al., “An Online EHW Pattern Recognition System Applied to Face Image Recognition”, University of Oslo, Norway; 2007. [cited by applicant]

Kawai et al., “An Adaptive Pattern Recognition Hardware with On-chip Shift Register-based Partial Reconfiguration”, IEEE; 2008. [cited by applicant]

Kutrib et al., “Massively Parallel Pattern Recognition with Link Features”, IFIG Research Report 0003; 2000. [cited by applicant]

Marculescu et al., Power Management of Multi-Core Systems: Challenges, Approaches, and Recent Developments Tutorial at ASPLOS, London, UK [online], Mar. 4, 2012. [cited by applicant]

Vitanen et al., “Image Pattern Recognition Using Configurable Logic Cell Array”, To Appear in Proc Computer Graphics International, Leeks UK; 1989. [cited by applicant]

Yasunaga et al., “Kernel-based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables”, IEEE; 2000. [cited by applicant]

U.S. Appl. No. 62/652,738, filed Feb. 12, 2005, Harris. [cited by applicant]

U.S. Appl. No. 61/788,364, filed Mar. 15, 2013, Brown et al. [cited by applicant]