IP Library Granted Patent US 7,292,572
Granted Patent B2
US 7,292,572 · App. 10/316,344 · Granted Nov 6, 2007

Multi-level register bank based configurable ethernet frame parser

Assignee: LSI Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,292,572
App. No.
10/316,344
Granted
Nov 6, 2007
Kind
B2
Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of match signals in response to an incoming data signal. Each match signal is generated in response to different search criteria. The second circuit may be configured to present a protocol indication signal in response to the plurality of match signals.

Claims (43)

1. An apparatus comprising:

a memory configured to store a plurality of pattern sets, each of said pattern sets respectively comprising an index value and a data value;

a first pattern matching circuit configured to (i) generate a first pointer to read a first set of said pattern sets and (ii) assert a first of a plurality of match signals in response to both a first position and a first content of a first unit of an incoming data signal matching both said index value and said data value of said first set;

a second pattern matching circuit configured to (i) generate a second pointer to read a second set of said pattern sets and (ii) assert a second of said match signals in response to both a second position and a second content of a second unit of said incoming data signal matching both said index value and said data value of said second set; and

a results circuit configured to assert a protocol indication signal in response to assertion of at least one of said match signals.

2. The apparatus according to claim 1 , wherein said first pattern matching circuit is further configured to seek a protocol of said incoming data signal at first level of a multi-level pattern and said second pattern matching circuit is further configured to seek said protocol at a second level of said multi-level pattern.

3. The apparatus according to claim 2 , further comprising:

a third pattern matching circuit configured to seek said protocol at a third level of said multi-level pattern.

4. The apparatus according to claim 3 , wherein said first pattern matching circuit, said second pattern matching circuit and said third pattern matching circuit simultaneously search said incoming data signal.

5. The apparatus according to claim 3 , wherein:

said first pattern matching circuit comprises a first state machine;

said second pattern matching circuit comprises a second state machine; and

said third pattern matching circuit comprises a third state machine.

6. The apparatus according to claim 5 , wherein

said third state machine compares said incoming data signal with information stored in a third set of said pattern sets.

7. The apparatus according to claim 5 , wherein said first state machine defines a plurality of states comprising a no match state, a match in progress state, a matched state and an increment said first pointer state.

8. The apparatus according to claim 1 , wherein said results circuit is further configured to assert said protocol indication signal in response to assertion of all of said match signals.

9. The apparatus according to claim 1 , wherein a plurality of search criteria stored in said pattern sets are configurable after fabrication of said apparatus has been completed.

10. The apparatus according to claim 9 , wherein each of said search criteria are independently configurable.

11. An apparatus comprising:

means for storing a plurality of pattern sets, each of said pattern sets respectively comprising an index value and a data value;

means for (i) generating a first pointer to read a first set of said pattern sets and (ii) asserting a first of a plurality of match signals in response to both a first position and a first content of a first unit of an incoming data signal matching both said index value and said data value of said first set;

means for (i) generating a second pointer to read a second set of said pattern sets and (ii) asserting a second of said match signals in response to both a second position and a second content of a second unit of said incoming data signal matching both said index value and said data value of said second set; and

means for asserting a protocol indication signal in response to assertion of at least one of said match signals.

12. The apparatus according to claim 11 , wherein said means for storing contains:

a first search criteria of a first protocol;

a second search criteria of a second protocol; and

a third search criteria of a third protocol, wherein each of said means for generating simultaneously search said incoming data signal.

13. A method for determining a protocol from an incoming data signal apparatus comprising:

(A) reading a first set of a plurality of pattern sets from a table in response to a first pointer, each of said pattern sets respectively comprising an index value and a data value;

(B) asserting a first of a plurality of match signals in response to both a first position and a first content of a first unit of said incoming data signal matching both said index value and said data value of said first set;

(C) reading a second set of said pattern sets from said table in response to a second pointer;

(D) asserting a second of said match signals in response to both a second position and a second content of a second unit of said incoming data signal matching both said index value and said data value of said second set; and

(E) asserting a protocol indication signal in response to assertion of at least one of said match signals.

14. The method according to claim 13 , wherein step (B) comprises searching for a first criteria in said incoming data signal and step (D) comprises searching for a second criteria in said incoming data signal.

15. The method according to claim 14 , wherein each of said searching steps occur simultaneously.

16. The method according to claim 13 , wherein step (B) seeks a protocol of said incoming data signal at a first level of a multi-level pattern and step (D) seeks said protocol at a second level of said multi-level pattern.

17. The method according to claim 13 , wherein said pattern sets further comprise a respective pattern value indicating a start of pattern, a continuation of pattern, an end of pattern and a start-and-end of pattern.

18. The method according to claim 13 , wherein said pattern sets further comprise a respective comparison value indicating one of (i) an equality operation and (ii) a less than or equal operation to be used in searching said incoming data signal.

19. The method according to claim 13 , wherein said index value defines an offset of a position in a payload of said incoming data signal.

20. The method according to claim 13 , further comprising the steps of:

reading a third set of said pattern sets from said table in response to a third pointer; and

asserting a third of said match signals in response to both said first position and said first content of said first unit of said incoming data signal matching both said index value and said data value of said third set.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2002
From: LIU, HONGPING; SU, ZHIQIANG J.
To: LSI LOGIC CORPORATION
Reel/Frame 013572/0952 →
Continuity (1)
Related Publication 20040125807A1 · Jul 1, 2004