IP Library › Granted Patent US 12,513,903
Granted Patent B2
US 12,513,903 · App. 17/966,594 · Granted Dec 30, 2025

Method for manufacturing a memory structure having stacked data lines and conductive structures on sides thereof

Inventors: Darwin A. Clampitt (Wilder, ID); Roger W. Lindsay (Boise, ID); Christopher R. Ritchie (Boise, ID); Shawn D. Lyonsmith (Boise, ID); Matthew J. King (Boise, ID); Lisa M. Clampitt (Boise, ID)
H10B43/27G11C7/18H01L21/02164H01L21/0217H01L21/31111H01L21/31144H01L21/76837H01L21/76885H01L23/5226H01L23/528H10B41/10H10B41/27H10B41/35H10B41/50H10B43/10H10B43/35H10B43/50
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Quick Facts
Patent No.
US 12,513,903
App. No.
17/966,594
Granted
Dec 30, 2025
Kind
B2
Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.

Claims (44)

1 . A method comprising:

forming levels of conductive materials stacked over one another and located over a conductive contact;

forming levels of dielectric materials interleaved with the levels of the conductive materials;

forming a conductive structure contacting the conductive contact and contacting a level of conductive material of the levels of conductive materials, wherein the conductive contact contacts a conductive pillar of a memory cell string of a memory device, and the memory cell string is formed before the levels of conductive materials and the levels of dielectric materials are formed; and

forming a dielectric structure electrically separating the conductive structure from the levels of conductive materials except the level of conductive material.

2 . The method of claim 1 , wherein the dielectric structure is formed before the conductive structure is formed.

3 . The method of claim 1 , further comprising:

forming an additional conductive structure contacting an additional conductive contact of an additional conductive pillar of an additional memory cell string of the memory device and contacting an additional level of conductive material of the levels of conductive materials; and

forming an additional dielectric structure electrically separating the additional conductive structure from the levels of conductive materials except the additional level of conductive material.

4 . The method of claim 3 , wherein the levels of conductive materials and the levels of dielectric materials form a stack of materials, the conductive structure is formed on a first side of the stack of the materials, and the additional conductive structure is formed on a second side of the stack of the materials.

5 . The method of claim 1 , further comprising:

forming additional conductive structures contacting respective additional conductive pillars of additional memory cell strings of the memory device and contacting additional levels of conductive materials of the levels of conductive materials; and

forming dielectric structures electrically separating the conductive structure and the additional conductive structures from the levels of conductive materials.

6 . The method of claim 5 , wherein the levels of conductive materials and the levels of dielectric materials form a stack of materials, and the conductive structure and the additional conductive structures are alternatively formed on sides of the stack of materials.

7 . A method comprising:

forming levels of first dielectric materials and levels of second dielectric materials interleaved with the levels of first dielectric materials, the levels of first dielectric materials and the levels of second dielectric materials are formed over conductive contacts of pillars of memory cell strings;

forming hard masks over the levels of first dielectric materials and the levels of second dielectric materials;

removing first portions of the levels of first dielectric materials and first portions of the levels of second dielectric materials to form a first staircase structure and a second staircase structure in a remaining portion of the levels of first dielectric materials and a remaining portion of the levels of second dielectric materials, wherein second portions of the levels of first dielectric materials under the hard mask and second portions of the levels of second dielectric materials under the hard mask are not removed when the first and second staircase structures are formed;

forming stacks of materials, such that the each of the stacks of materials includes a portion of the first staircase structure, a portion of the second staircase structure, and one of the second portions of the levels of first dielectric materials and the second portions of the levels of second dielectric materials;

removing the remaining portion of the levels of second dielectric materials in the first and second staircase structures, and the second portions of the levels of second dielectric materials under the hard mask;

forming a conductive material in spaces where the remaining portion of the levels of second dielectric materials in the first and second staircase structures and the second portions of the levels of second dielectric materials under the hard mask were removed; and

forming conductive structures such that a respective conductive structure of the conductive structures contacts a respective conductive material in one of the stacks of materials.

8 . The method of claim 7 , wherein the levels of first dielectric materials comprise silicon dioxide and the levels of second dielectric materials comprise silicon nitride.

9 . The method of claim 7 , wherein the second staircase structure is opposite from the first staircase structure.

10 . The method of claim 7 , further comprising:

forming dielectric spacers between the conductive structures and the stacks of materials to separate the conductive structures from the conductive material.

11 . The method of claim 7 , wherein top exposed portions of the first remaining portion of the levels of second dielectric materials of the first staircase structure are at uneven levels with the top exposed portions of the first remaining portion of the levels of second dielectric materials of the second staircase structure.

12 . A method comprising:

forming levels of first dielectric materials and levels of second dielectric materials interleaved with the levels of first dielectric materials, the levels of first dielectric materials and the levels of second dielectric materials are formed over conductive contacts of pillars of memory cell strings;

removing portions of the levels of first dielectric materials and portions of the levels of second dielectric materials to form stacks of materials, the stacks of materials separated from each other such that the each of the stacks of materials includes respective remaining portions of the levels of first dielectric materials and respective remaining portions of second portions of the levels of second dielectric materials;

removing the remaining portions of the levels of second dielectric materials in the stacks of materials;

forming a conductive material in spaces where the remaining portions of the levels of second dielectric materials in the stacks of materials were removed to form levels of conductive materials interleaved with the remaining portions of the levels of first dielectric materials, the levels of conductive materials interleaved with the remaining portions of the levels of first dielectric materials forming separate stacks of levels of conductive materials interleaved with the remaining portions of the levels of first dielectric materials; and

forming conductive structures such that a respective conductive structure of the conductive structures contacts a respective level of the levels of conductive materials in the stacks of levels of conductive materials interleaved with the remaining portions of the levels of first dielectric materials.

13 . The method of claim 12 , wherein the levels of first dielectric materials comprise silicon dioxide.

14 . The method of claim 12 , wherein the levels of second dielectric materials comprise silicon nitride.

15 . The method of claim 12 , wherein the conductive structures include:

a first conductive structure formed on a first side of a stack among the stacks of levels of conductive materials interleaved with the remaining portions of the levels of first dielectric materials; and

a second conductive structure formed on a second side of the stack.

16 . The method of claim 15 , wherein:

the levels of conductive materials interleaved with the remaining portions of the levels of first dielectric materials in the stack include a first level, the first level including a first protrusion; and

the levels of conductive materials interleaved with the remaining portions of the levels of first dielectric materials in the stack include a second level, the second level including a second protrusion.

17 . The method of claim 16 , wherein the first and second protrusions are located on opposite sides of the stack.

18 . The method of claim 15 , wherein the first and second conductive structures contact different levels of conductive materials among the levels of conductive materials in the stack.

19 . The method of claim 18 , wherein the first and second conductive structures contact different conductive contacts among the conductive contacts of pillars of memory cell strings.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP, LLC
Reel/Frame 065050/0391 →
Continuity (2)
Division 16664280 · Oct 25, 2019
Related Publication 20230043786A1 · Feb 9, 2023
References Cited (182)
US 5453955A · Sakui et al. · 1995 [cited by applicant]
US 6058044A · Sugiura et al. · 2000 [cited by applicant]
US 6304479B1 · Vollrath et al. · 2001 [cited by applicant]
US 6751124B2 · Lee · 2004 [cited by applicant]
US 7243185B2 · See et al. · 2007 [cited by applicant]
US 7355237B2 · Lutze et al. · 2008 [cited by applicant]
US 7807533B2 · Lutze et al. · 2010 [cited by applicant]
US 7978517B2 · Isobe · 2011 [cited by applicant]
US 8294131B2 · Kim et al. · 2012 [cited by applicant]
US 8368137B2 · Mokhlesi et al. · 2013 [cited by applicant]
US 8369142B2 · Futatsuyama · 2013 [cited by applicant]
US 8441855B2 · Liu · 2013 [cited by applicant]
US 8614918B2 · Sakui · 2013 [cited by applicant]
US 8619471B2 · Tanzawa · 2013 [cited by applicant]
US 8780631B2 · Tanzawa · 2014 [cited by applicant]
US 8811084B2 · Tanzawa · 2014 [cited by applicant]
US 8890233B2 · Hung et al. · 2014 [cited by applicant]
US 8902663B1 · Or-Bach et al. · 2014 [cited by applicant]
US 9036421B2 · Liu · 2015 [cited by applicant]
US 9093152B2 · Sakui et al. · 2015 [cited by applicant]
US 9147493B2 · Sakui · 2015 [cited by applicant]
US 9159736B2 · Vu et al. · 2015 [cited by applicant]
US 9711224B2 · Tanzawa · 2017 [cited by applicant]
US 9734915B2 · Sakui · 2017 [cited by applicant]
US 10170188B1 · Yip · 2019 [cited by applicant]
US 10242746B2 · Sakui et al. · 2019 [cited by applicant]
US 10643714B2 · Sakui · 2020 [cited by applicant]
US 11075163B2 · Sakui et al. · 2021 [cited by applicant]
US 11508746B2 · Clampitt et al. · 2022 [cited by applicant]
US 11605588B2 · Moschiano et al. · 2023 [cited by applicant]
US 20050180186A1 · Lutze et al. · 2005 [cited by applicant]
US 20070096254A1 · Ritter et al. · 2007 [cited by applicant]
US 20070158736A1 · Arai et al. · 2007 [cited by applicant]
US 20080084729A1 · Cho et al. · 2008 [cited by applicant]
US 20080157169A1 · Yuan · 2008 [cited by applicant]
US 20080160680A1 · Yuan · 2008 [cited by applicant]
US 20090067236A1 · Isobe et al. · 2009 [cited by applicant]
US 20090238005A1 · You · 2009 [cited by applicant]
US 20090251962A1 · Yun et al. · 2009 [cited by applicant]
US 20090268523A1 · Maejima · 2009 [cited by applicant]
US 20100036600A1 · Shinmyoh et al. · 2010 [cited by applicant]
US 20100322000A1 · Shim et al. · 2010 [cited by applicant]
US 20110002178A1 · Hwang et al. · 2011 [cited by applicant]
US 20110013458A1 · Seol · 2011 [cited by applicant]
US 20110266604A1 · Kim et al. · 2011 [cited by applicant]
US 20110299314A1 · Samachisa et al. · 2011 [cited by applicant]
US 20110310673A1 · Cho et al. · 2011 [cited by applicant]
US 20120001249A1 · Alsmeier et al. · 2012 [cited by applicant]
US 20120044733A1 · Scheuerlein · 2012 [cited by applicant]
US 20120063231A1 · Wood et al. · 2012 [cited by applicant]
US 20120081958A1 · Lee et al. · 2012 [cited by applicant]
US 20120140549A1 · Maejima · 2012 [cited by applicant]
US 20120182805A1 · Liu · 2012 [cited by applicant]
US 20120257433A1 · Yan et al. · 2012 [cited by applicant]
US 20140119117A1 · Sakui · 2014 [cited by examiner]
US 20140369116A1 · Sakui · 2014 [cited by applicant]
US 20150048434A1 · Rhie · 2015 [cited by applicant]
US 20150162084A1 · Morooka et al. · 2015 [cited by applicant]
US 20150333001A1 · Sakui et al. · 2015 [cited by applicant]
US 20160019970A1 · Sakui · 2016 [cited by applicant]
US 20170365615A1 · Dennison et al. · 2017 [cited by applicant]
US 20180068794A1 · Lee et al. · 2018 [cited by applicant]
US 20180122482A1 · Sakui · 2018 [cited by applicant]
US 20180295715A1 · Tsukuda et al. · 2018 [cited by applicant]
US 20190237475A1 · Jung et al. · 2019 [cited by applicant]
US 20190279722A1 · Sakui · 2019 [cited by applicant]
US 20210066277A1 · Kim · 2021 [cited by examiner]
US 20210126007A1 · Clampitt et al. · 2021 [cited by applicant]
US 20210193570A1 · Moschiano et al. · 2021 [cited by applicant]
CN 102237368A · 2011 [cited by applicant]
CN 102623456A · 2012 [cited by applicant]
CN 104813406A · 2015 [cited by applicant]
CN 109950198A · 2019 [cited by applicant]
CN 104813406B · 2020 [cited by applicant]
CN 111402941A · 2020 [cited by applicant]
CN 112713148A · 2021 [cited by applicant]
CN 113012740A · 2021 [cited by applicant]
JP 2009124107A · 2009 [cited by applicant]
KR 20110132820A · 2011 [cited by applicant]
KR 101102548B1 · 2012 [cited by applicant]
KR 20120013971A · 2012 [cited by applicant]
KR 20120084268A · 2012 [cited by applicant]
KR 20120122673A · 2012 [cited by applicant]
TW 201432693A · 2014 [cited by applicant]
TW I735404B · 2021 [cited by applicant]
WO WO2014066837A1 · 2014 [cited by applicant]
U.S. Appl. No. 13/661,498, Restriction Requirement mailed Mar. 27, 2014, 7 pgs. [cited by applicant]
U.S. Appl. No. 13/661,498, Response filed May 7, 2014 to Restriction Requirement mailed Mar. 27, 2014, 10 pgs. [cited by applicant]
U.S. Appl. No. 13/661,498, Non Final Office Action mailed Jul. 8, 2014, 14 pgs. [cited by applicant]
U.S. Appl. No. 13/661,498, Response filed Oct. 8, 2014 to Non Final Office Action mailed Jul. 8, 2014, 13 pgs. [cited by applicant]
U.S. Appl. No. 13/661,498, Final Office Action mailed Jan. 2, 2015, 18 pgs. [cited by applicant]
U.S. Appl. No. 13/661,498, Response to Office Action mailed Jan. 2, 2015, 14 pgs. [cited by applicant]
U.S. Appl. No. 13/661,498, Notice of Allowance mailed Mar. 20, 2015, 11 pgs. [cited by applicant]
U.S. Appl. No. 13/919,599, Non Final Office Action mailed Jan. 5, 2015, 9 pgs. [cited by applicant]
U.S. Appl. No. 13/919,599, Response filed Apr. 1, 2015 to Non Final Office Action mailed Jan. 5, 2015, 12 pgs. [cited by applicant]
U.S. Appl. No. 13/919,599, Notice of Allowance mailed May 18, 2015, 9 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Non final Office Action mailed Jul. 25, 2016, 15 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Response filed Oct. 25, 2016 to Non Final Office Action mailed Jul. 25, 2016, 12 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Final Office Action mailed Mar. 3, 2017, 15 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Response filed Jun. 5, 2017 to Final Office Action mailed Mar. 3, 2017, 9 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Advisory Action mailed Jul. 3, 2017, 3 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Response filed Aug. 3, 2017 to Final Office Action mailed Mar. 3, 2017, 11 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Advisory Action mailed Aug. 31, 2017, 3 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Non final Office Action mailed Nov. 3, 2017, 17 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Response filed Jan. 31, 2018 to Non Final Office Action mailed Nov. 3, 2017, 11 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Final Office Action mailed Aug. 29, 2018, 18 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Response filed Jan. 29, 2019 to Final Office Action mailed Aug. 29, 2018, 11 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Non Final Office Action mailed May 13, 2019, 13 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Response filed Oct. 15, 2019 to Non-Final Office Action mailed May 13, 2019, 14 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Final Office Action mailed Nov. 7, 2019, 14 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Response filed Mar. 9, 2020 to Final Office Action mailed Nov. 7, 2019, 6 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Notice of Allowance mailed Mar. 25, 2020, 9 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Non Final Office Action mailed Aug. 4, 2020, 11 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Response filed Nov. 4, 2020 to Non Final Office Action mailed Aug. 4, 2020, 13 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Final Office Action mailed Dec. 14, 2020, 14 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Response filed Mar. 15, 2021 to Final Office Action mailed Dec. 14, 2020, 11 pgs. [cited by applicant]
U.S. Appl. No. 14/810,044, Notice of Allowance mailed Mar. 24, 2021, 9 pgs. [cited by applicant]
U.S. Appl. No. 14/867,948, Non Final Office Action mailed Jan. 21, 2016, 9 pgs. [cited by applicant]
U.S. Appl. No. 14/867,948, Response filed Apr. 21, 2016 to Non Final Office Action mailed Jan. 21, 2016, 9 pgs. [cited by applicant]
U.S. Appl. No. 14/867,948, Notice of Allowance mailed Aug. 19, 2016, 9 pgs. [cited by applicant]
U.S. Appl. No. 14/867,948, Notice of Allowance mailed Dec. 19, 2016, 11 pgs. [cited by applicant]
U.S. Appl. No. 14/867,948, Notice of Allowance mailed Apr. 5, 2017, 10 pgs. [cited by applicant]
U.S. Appl. No. 15/676,659, Non Final Office Action mailed Feb. 23, 2018, 15 pgs. [cited by applicant]
U.S. Appl. No. 15/676,659, Response filed May 23, 2018 to Non-Final Office Action mailed Feb. 23, 2018, 9 pgs. [cited by applicant]
U.S. Appl. No. 15/676,659, Notice of Allowance mailed Aug. 1, 2018, 10 pgs. [cited by applicant]
U.S. Appl. No. 15/676,659, Notice of Allowability mailed Aug. 29, 2018, 2 pgs. [cited by applicant]
U.S. Appl. No. 15/676,659, Notice of Allowance mailed Nov. 5, 2018, 11 pgs. [cited by applicant]
U.S. Appl. No. 15/676,659, Notice of Allowability mailed Feb. 6, 2019, 2 pgs. [cited by applicant]
U.S. Appl. No. 16/275,038, Preliminary Amendment filed Jun. 5, 2019, 8 pgs. [cited by applicant]
U.S. Appl. No. 16/275,038, Non Final Office Action mailed Aug. 21, 2019, 22 pgs. [cited by applicant]
U.S. Appl. No. 16/275,038, Response filed Nov. 20, 2019 to Non-Final Office Action mailed Aug. 21, 2019, 11 pgs. [cited by applicant]
U.S. Appl. No. 16/275,038, Notice of Allowance mailed Dec. 30, 2019, 11 pgs. [cited by applicant]
U.S. Appl. No. 16/664,280, Restriction Requirement mailed May 26, 2021, 7 pgs. [cited by applicant]
U.S. Appl. No. 16/664,280, Response filed Jul. 26, 2021 to Restriction Requirement mailed May 26, 2021, pgs. [cited by applicant]
U.S. Appl. No. 16/664,280, Non Final Office Action mailed Aug. 12, 2021, 14 pgs. [cited by applicant]
U.S. Appl. No. 16/664,280, Response filed Nov. 12, 2021 to Non Final Office Action mailed Aug. 12, 2021, 11 pgs. [cited by applicant]
U.S. Appl. No. 16/664,280, Notice of Allowance mailed Feb. 22, 2022, 10 pgs. [cited by applicant]
U.S. Appl. No. 16/664,280, Non Final Office Action mailed Mar. 24, 2022, 12 pgs. [cited by applicant]
U.S. Appl. No. 16/664,280, Response filed Jun. 24, 2022 to Non Final Office Action mailed Mar. 24, 2022, pgs. [cited by applicant]
U.S. Appl. No. 16/664,280, Notice of Allowance mailed Jul. 19, 2022, 11 pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Restriction Requirement mailed Nov. 4, 2020, 6 pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Response filed Jan. 4, 2021 to Restriction Requirement mailed Nov. 4, 2020, pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Non Final Office Action mailed Apr. 1, 2021, 16 pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Response filed Jul. 1, 2021 to Non Final Office Action mailed Apr. 1, 2021, pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Final Office Action mailed Oct. 8, 2021, 13 pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Response filed Dec. 8, 2021 to Final Office Action mailed Oct. 8, 2021, 8 pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Advisory Action mailed Dec. 21, 2021, 4 pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Response filed Jan. 7, 2022 to Advisory Action mailed Dec. 21, 2021 and Final Office Action mailed Oct. 8, 2021, 8 pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Non Final Office Action mailed Apr. 25, 2022, 13 pgs. [cited by applicant]
U.S. Appl. No. 16/723,758, Response filed Jul. 25, 2022 to Non Final Office Action mailed Apr. 25, 2022, pgs. [cited by applicant]
“Chinese Application Serial No. 202010162449.3, Office Action mailed Mar. 17, 2023”, with WIPO machine English translation, 18 pages. [cited by applicant]
U.S. Appl. No. 13/661,498 U.S. Pat. No. 9,093,152, filed Oct. 26, 2012, Multiple Data Line Memory and Methods. [cited by applicant]
U.S. Appl. No. 14/810,044 U.S. Pat. No. 11,075,163, filed Jul. 27, 2015, Vertical NAND String Multiple Data Line Memory. [cited by applicant]
U.S. Appl. No. 13/919,599 U.S. Pat. No. 9,147,493, filed Jun. 17, 2013, Memory Operations in a Shielded Vertically Stacked Data Line Architecture. [cited by applicant]
U.S. Appl. No. 14/867,948 U.S. Pat. No. 9,734,915, filed Sep. 28, 2015, Shielded Vertically Stacked Data Line Architecture for Memory. [cited by applicant]
U.S. Appl. No. 15/676,659 U.S. Pat. No. 10,242,746, filed Aug. 14, 2017, Shielded Vertically Stacked Data Line Architecture for Memory. [cited by applicant]
U.S. Appl. No. 16/275,038 U.S. Pat. No. 10,643,714, filed Feb. 13, 2019, Shielded Vertically Stacked Data Line Architecture for Memory. [cited by applicant]
U.S. Appl. No. 16/723,758, filed Dec. 20, 2019, Memory Device Including Data lines on Multiple Device levels. [cited by applicant]
U.S. Appl. No. 16/664,280, filed Oct. 25, 2019, Semiconductor Device having a stack of Data Lines With Conductive Structures on Both Sides Thereof. [cited by applicant]
“A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology”, IEEE Journal of Solid-State Circuits, 44(1), (Jan. 2009), 186-193. [cited by applicant]
“Chinese Application Serial No. 201380062063.3, Office Action mailed May 13, 2019”, w/ English translation, 21 pgs. [cited by applicant]
“Chinese Application Serial No. 201380062063.3, Office Action mailed Jun. 22, 2018”, w/ English translation, 21 pgs. [cited by applicant]
“Chinese Application Serial No. 201380062063.3, Response filed Jul. 26, 2019 to Office Action mailed May 13, 2019”, w/ English Claims, 34 pgs. [cited by applicant]
“Chinese Application Serial No. 201380062063.3, Response filed Nov. 7, 2018 to Office Action mailed Jun. 22, 2018”, w/ English Claims, 24 pgs. [cited by applicant]
“International Application Serial No. PCT/US2013/066941, International Preliminary Report on Patentability mailed May 7, 2015”, 9 pgs. [cited by applicant]
“International Application Serial No. PCT/US2013/066941, International Search Report mailed Feb. 10, 2014”, 3 pgs. [cited by applicant]
“International Application Serial No. PCT/US2013/066941, Written Opinion mailed Feb. 10, 2014”, 7 pgs. [cited by applicant]
“Korean Application Serial No. 10-2015-7013601, Final Office Action mailed Jul. 29, 2021”, w/ English translation, 7 pgs. [cited by applicant]
“Korean Application Serial No. 10-2015-7013601, Notice of Preliminary Rejection mailed Dec. 18, 2019”, w/ English Translation, 9 pgs. [cited by applicant]
“Korean Application Serial No. 10-2015-7013601, Notice of Preliminary Rejection mailed Dec. 29, 2020”, w/ English translation, 11 pgs. [cited by applicant]
“Korean Application Serial No. 10-2015-7013601, Response filed Mar. 2, 2021 to Notice of Preliminary Rejection mailed Dec. 29, 2020”, w/ English Claims, 15 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, Decision of Rejection mailed Oct. 12, 2018”, w/ English translation, 11 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, First Office Action mailed Feb. 14, 2020”, w/ English tranlsation, 32 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, Office Action mailed Jul. 11, 2017”, No English Translation, 12 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, Office Action mailed Sep. 22, 2020”, w/ English Translation, 21 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, Office Action mailed Nov. 22, 2017”, With English Translation, 31 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, Response filed Feb. 22, 2018 to Office Action mailed Nov. 22, 2017”, w/English Claims, 15 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, Response filed Mar. 25, 2021 to Office Action mailed Sep. 22, 2020”, w/ English Claims, 17 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, Response filed Apr. 16, 2019 to Decision of Rejection mailed Oct. 12, 2018”, w/ English Claims, 16 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, Response filed Jun. 22, 2020 to First Office Action mailed Feb. 14, 2020”, w/ English Claims, 18 pgs. [cited by applicant]
“Taiwanese Application Serial No. 102138789, Response Filed Oct. 12, 2017 to Office Action mailed Jul. 11, 2017”, w/English Claims, 13 pgs. [cited by applicant]
Nakano, H, et al., “A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMS”, Symposium on VLSI Circuits, Digest of Technical Papers., (Jun. 1996). [cited by applicant]