Correct-by-construction filler cell insertion
This application discloses a computing system implementing a yield enhancer tool to extract characteristics of cells from a physical layout design for an integrated circuit, determine locations of vacant regions in the physical layout design, apply electrical design rules for manufacture of the integrated circuit to the extracted characteristics in order to identify cells in the physical layout design that would violate the electrical design rules. The computing system can select filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and the electrical design rules, and insert the selected filler cells in the vacant regions of the physical design layout. The computing system can perform a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.
1 . A method comprising:
extracting, by a computing system, characteristics of cells from a physical layout design for an integrated circuit;
determining, by the computing system, locations of vacant regions in the physical layout design;
selecting, by the computing system, filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and one or more electrical design rules for manufacture of the integrated circuit;
generating, by the computing system, a reference cell for each of the selected filler cells, wherein each reference cell corresponds to an empty cell having a name of the corresponding selected filler cell;
populating, by the computing system, the vacant regions in the physical layout design with reference cells associated with the selected filler cells; and
replacing, by the computing system, the reference cells populated in the physical layout design with the selected filler cells based, at least in part, on the names in the reference cells.
2 . The method of claim 1 , wherein selecting the filler cells for the vacant regions further comprises:
identifying one or more of the cells in the physical layout design have sizes that would violate at least one of the electrical design rules;
determining sizes and types of the filler cells that, when placed adjacent to the identified cells in the physical layout design, would eliminate electrical design rule violations; and
selecting the filler cells for at least a subset of the vacant regions based, at least in part, on the determined sizes and types of the filler cells.
3 . The method of claim 2 , wherein, after selecting the filler cells for at least the subset of the vacant regions, identifying another subset of the vacant regions in the physical layout design and selecting the filler cells for the other subset of the vacant regions.
4 . The method of claim 1 , wherein replacing the reference cells with the selected filler cells further comprises:
searching a filler cell library using the names in the reference cells to identify the selected filler cells; and
inserting the selected filler cells from the filler cell library into locations of the physical design layout previously occupied by the cell references.
5 . The method of claim 1 , further comprising performing, by the computing system, a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.
6 . The method of claim 1 , wherein the extracted characteristics of the cells abutting the vacant regions include at least one of threshold voltages of the cells and the sizes of the cells.
7 . A system comprising:
a memory system configured to store computer-executable instructions; and
a computing system, in response to execution of the computer-executable instructions, is configured to:
extract characteristics of cells from a physical layout design for an integrated circuit;
determine locations of vacant regions in the physical layout design;
select filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and one or more electrical design rules for manufacture of the integrated circuit;
generate a reference cell for each of the selected filler cells, wherein each reference cell corresponds to an empty cell having a name of the corresponding selected filler cell;
populate the vacant regions in the physical layout design with reference cells associated with the selected filler cells; and
replace the reference cells populated in the physical layout design with the selected filler cells based, at least in part, on the names in the reference cells.
8 . The system of claim 7 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to select the filler cells for the vacant regions by:
identifying one or more of the cells in the physical layout design have sizes that would violate at least one of the electrical design rules;
determining sizes and types of the filler cells that, when placed adjacent to the identified cells in the physical layout design, would eliminate electrical design rule violations; and
selecting the filler cells for at least a subset of the vacant regions based, at least in part, on the determined sizes and types of the filler cells.
9 . The system of claim 8 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to, after selecting the filler cells for at least the subset of the vacant regions, identify another subset of the vacant regions in the physical layout design and select the filler cells for the other subset of the vacant regions.
10 . The system of claim 7 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to replace the reference cells with the selected filler cells by:
searching a filler cell library using the names in the reference cells to identify the selected filler cells; and
inserting the selected filler cells from the filler cell library into locations of the physical design layout previously occupied by the cell references.
11 . The system of claim 7 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: perform a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.
12 . An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
extracting characteristics of cells from a physical layout design for an integrated circuit;
determining locations of vacant regions in the physical layout design;
selecting filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and one or more electrical design rules for manufacture of the integrated circuit;
generating a reference cell for each of the selected filler cells, wherein each reference cell corresponds to an empty cell having a name of the corresponding selected filler cell;
populating the vacant regions in the physical layout design with reference cells associated with the selected filler cells; and
replacing the reference cells populated in the physical layout design with the selected filler cells based, at least in part, on the names in the reference cells.
13 . The apparatus of claim 12 , wherein selecting the filler cells for the vacant regions further comprises:
identifying one or more of the cells in the physical layout design have sizes that would violate at least one of the electrical design rules;
determining sizes and types of the filler cells that, when placed adjacent to the identified cells in the physical layout design, would eliminate electrical design rule violations; and
selecting the filler cells for at least a subset of the vacant regions based, at least in part, on the determined sizes and types of the filler cells.
14 . The apparatus of claim 13 , wherein, after selecting the filler cells for at least the subset of the vacant regions, identifying another subset of the vacant regions in the physical layout design and selecting the filler cells for the other subset of the vacant regions.
15 . The apparatus of claim 12 , wherein replacing the reference cells with the selected filler cells further comprises:
searching a filler cell library using the names in the reference cells to identify the selected filler cells; and
inserting the selected filler cells from the filler cell library into locations of the physical design layout previously occupied by the cell references.
16 . The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising performing a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.
17 . The apparatus of claim 12 , wherein the extracted characteristics of the cells abutting the vacant regions include at least one of threshold voltages of the cells and the sizes of the cells.