Method of optimizing customizable filler cells in an integrated circuit physical design process
View Patent ↗A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.
1. A method of moving placement of logic cells within a first region having a plurality of tracks, the method comprising:
providing a circuit layout having a first region with a plurality of logic cells and a plurality of filler cells proximate ones of said plurality of logic cells, each of said plurality of filler cells having a width that is less than a width W 1 ; and
moving ones of said plurality of logic cells so as to combine ones of said plurality of filler cells to form at least one customizable filler cell having a width of at least W 1 .
2. The method according to claim 1 , wherein each one of the plurality of tracks has a width W 2 and said moving step is performed so that said width W 1 exceeds said width W 2 .
3. The method according to claim 2 , wherein said plurality of tracks includes at least four tracks.
4. The method according to claim 3 , further comprising converting said at least one customizable filler cell into a combinatorial logic gate following a completion of said circuit layout.
5. The method according to claim 3 , wherein said moving step is performed such tat said ones of said plurality of logic cells are located in said first region.
6. The method according to claim 1 , further comprising rerouting said logic cells within said first region after said moving step.
7. The method according to claim 1 , wherein said moving step involves moving each of said ones of said plurality of logic cells no more than a first amount.
8. The method according to claim 1 , wherein said first region is a row of logic cells, and said ones of plurality of logic cells are moved within said row.
9. The method according to claim 1 , wherein said first region is a column of logic cells and said ones of plurality of logic cells are moved within said column.
10. The method according to claim 1 , including the step of selecting said first region based on a need for said at least one customizable filler cell within said circuit layout.
11. The method according to claim 1 , wherein said moving step starts at a first location in said first region and said logic cells are moved in a first direction relative to said first location.
12. A method of laying out a logic macro, the method comprising:
synthesizing a logic macro having a plurality of logic cells arranged in a plurality of first regions, each of said plurality of first regions having a plurality of tracks, wherein one or more of said plurality of first regions has at least two sections without a logic cell;
placing at least some of said plurality of logic cells within said one or more of said plurality of first regions so as to combine said at least two sections into one section; and
routing wiring for said at least some of said plurality of logic cells.
13. The method according to claim 12 , wherein said placing step involves selecting one or more of said plurality of first regions as focus regions, and said placing step is performed with respect to ones of said plurality of logic cells in said focus regions.
14. The method according to claim 12 , wherein said placing step involves selecting one or more of said plurality of first regions as excluded regions, and said placing step is performed with respect to ones of said plurality of logic cells in said excluded regions.
15. The method according to claim 12 , wherein said placing step involves moving ones of said plurality of logic cells no more than a first distance so as to combine said at least two sections into one section.
16. A computer readable medium containing computer executable instructions implementing a method of moving placement of logic cells in a region having a plurality of tracks, the computer executable instructions comprising:
a first set of instructions for providing a circuit layout having a first region with a plurality of logic cells and a plurality of filler cells proximate ones of said plurality of logic cells, each of said plurality of filler cells having a width that is less than a width W 1 ; and
a second set of instructions for moving ones of said plurality of logic cells so as to combine ones of said plurality of filler cells in a manner forming at least one customizable filler cell having a width of at least W 1 .
17. The computer readable medium according to claim 16 , wherein each one of the plurality of tracks has a width W 2 and said second set of instructions is performed so that said width W 1 exceeds said width W 2 .
18. The computer readable medium according to claim 16 , wherein said second set of instructions is performed so that said width W 1 has a width exceeding four tracks.
19. The computer readable medium according to claim 16 , wherein said second set of instructions is performed so that said ones of said plurality of logic cells are located in said first region.
20. The computer readable medium according to claim 16 , wherein said second set of instructions is performed so that said width W 1 is large enough to accommodate a combinatorial or sequential logic gate.