Space optimization between SRAM cells and standard cells
A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.
1 . A structure comprising:
a plurality of standard cells located as a standard cell row;
a Static Random Access Memory (SRAM) array; and
a plurality of filler cells located as a filler cell row, wherein the filler cell row is between the standard cell row and the SRAM array, wherein the plurality of filler cells have a first height equal to a second height of an SRAM cell in the SRAM array, and wherein top boundaries of the plurality of filler cells are in contact with bottom boundaries of the plurality of standard cells, and additional bottom boundaries of the plurality of filler cells are in contact with an additional top boundary of the SRAM array.
2 . The structure of claim 1 , wherein the plurality of filler cells have identical layouts, and one of the plurality of filler cells has a first length equal to a second length of one of SRAM cells in the SRAM array.
3 . The structure of claim 1 , wherein the plurality of filler cells are dummy cells electrically disconnected from both of the plurality of standard cells and the SRAM array.
4 . The structure of claim 1 , wherein each of the plurality of filler cells comprises a semiconductor fin extending from a left boundary to a right boundary of a respective filler cell in the plurality of filler cells.
5 . The structure of claim 4 , wherein the semiconductor fins in the plurality of filler cells are joined to form a continuous fin, and the continuous fin has a length equal to a total length of all SRAM cells in a row of the SRAM array.
6 . The structure of claim 1 , wherein each of the plurality of filler cells comprises a plurality of semiconductor fins, and first neighboring fins closer to the plurality of standard cells have a first pitch, and second neighboring fins closer to the SRAM array have a second pitch smaller than the first pitch.
7 . The structure of claim 1 , wherein each of the plurality of filler cells comprises a gate feature continuously extending from top to bottom of a respective filler cell in the plurality of filler cells.
8 . The structure of claim 7 , wherein the gate feature is electrically floating.
9 . The structure of claim 1 , wherein each of the plurality of filler cells comprises a discontinuous gate feature, wherein the discontinuous gate feature comprises a first gate feature and a second gate feature aligned to a same straight line and disconnected from each other, and wherein the first gate feature extends to top of a respective filler cell in the plurality of filler cells, and the second gate feature extends to bottom of the respective filler cell in the plurality of filler cells.
10 . A structure comprising:
a plurality of standard cells located as a standard cell row;
a Static Random Access Memory (SRAM) array; and
a plurality of filler cells located as a filler cell row, wherein the filler cell row is between the standard cell row and the SRAM array, wherein the plurality of filler cells have a first height equal to a second height of an SRAM cell in the SRAM array, and wherein top boundaries of the plurality of filler cells are in contact with bottom boundaries of the plurality of standard cells, and additional bottom boundaries of the plurality of filler cells are in contact with an additional top boundary of the SRAM array, wherein each of the plurality of filler cells comprises:
a discontinuous gate feature, wherein the discontinuous gate feature comprises a first gate feature and a second gate feature aligned to a same straight line and disconnected from each other, and wherein the first gate feature extends to top of a respective filler cell in the plurality of filler cells, and the second gate feature extends to bottom of the respective filler cell in the plurality of filler cells.
11 . The structure of claim 10 , wherein the plurality of filler cells have identical layouts, and one of the plurality of filler cells has a first length equal to a second length of one of SRAM cells in the SRAM array.
12 . The structure of claim 10 , wherein the plurality of filler cells are dummy cells electrically disconnected from both of the plurality of standard cells and the SRAM array.
13 . The structure of claim 10 , wherein each of the plurality of filler cells comprises a semiconductor fin extending from a left boundary to a right boundary of a respective filler cell in the plurality of filler cells.
14 . The structure of claim 13 , wherein the semiconductor fins in the plurality of filler cells are joined to form a continuous fin, and the continuous fin has a length equal to a total length of all SRAM cells in a row of the SRAM array.
15 . The structure of claim 10 , wherein each of the plurality of filler cells comprises a plurality of semiconductor fins, and first neighboring fins closer to the plurality of standard cells have a first pitch, and second neighboring fins closer to the SRAM array have a second pitch smaller than the first pitch.
16 . The structure of claim 10 , wherein each of the plurality of filler cells comprises a gate feature continuously extending from top to bottom of a respective filler cell in the plurality of filler cells.
17 . The structure of claim 16 , wherein the gate feature is electrically floating.
18 . A structure comprising:
a plurality of standard cells located as a standard cell row;
a Static Random Access Memory (SRAM) array; and
a plurality of filler cells located as a filler cell row, wherein the filler cell row is between the standard cell row and the SRAM array, wherein the plurality of filler cells have a first height equal to a second height of an SRAM cell in the SRAM array, wherein top boundaries of the plurality of filler cells are in contact with bottom boundaries of the plurality of standard cells, and additional bottom boundaries of the plurality of filler cells are in contact with an additional top boundary of the SRAM array, wherein the plurality of filler cells have identical layouts, and one of the plurality of filler cells has a first length equal to a second length of one of SRAM cells in the SRAM array, and wherein each of the plurality of filler cells comprises a gate feature continuously extending from top to bottom of a respective filler cell in the plurality of filler cells.
19 . The structure of claim 1 , wherein the plurality of filler cells are dummy cells electrically disconnected from both of the plurality of standard cells and the SRAM array.
20 . The structure of claim 18 , wherein each of the plurality of filler cells comprises a semiconductor fin extending from a left boundary to a right boundary of a respective filler cell in the plurality of filler cells.