Synchronous controlled, self-timed local SRAM block
The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.
1. A method of forming a memory device comprising:
forming at least one synchronously controlled global element;
forming a plurality of self-timed local elements; and
interfacing at least one of said plurality of self-timed local elements with at least said synchronous controlled global element.
2. The method of claim 1 , wherein said at least one synchronously controlled global element comprises at least one of a global predecoder, a global decoder, a global controller and a global sense amplifier.
3. The method of claim 1 , wherein said plurality of self-timed local elements comprises a plurality of memory cells forming at least one cell array.
4. The method of claim 1 , wherein said plurality of self-timed local elements comprises at least one local decoder.
5. The memory device of claim 1 , wherein said plurality of self-timed local elements comprises at least one local sense amplifier.
6. The method of claim 1 , wherein said plurality of self-timed local elements comprises at least one cluster.
7. The method of claim 1 , wherein said plurality of self-timed local elements comprises at least one block.
8. The method of claim 7 , wherein said block comprises at least one sub-block.
9. The method of claim 1 comprising interfacing one of said plurality of self-timed local elements with at least one other of said plurality of self-timed local elements.
10. The method of claim 9 comprising interfacing at least one self-timed local decoder with a plurality of memory cells forming at least one cell array.
11. The method of claim 9 comprising interfacing at least one self-timed local sense amplifier with at least one self-timed local decoder and a plurality of memory cells forming at least one cell array.
12. The memory structure of claim 11 wherein said plurality of memory cells comprise at least one SRAM memory cell.
13. The memory structure of claim 11 wherein said plurality of memory cells comprise at least one DRAM memory cell.
14. The memory structure of claim 11 wherein said plurality of memory cells comprise at least one ROM memory cell.
15. The memory structure of claim 11 wherein said plurality of memory cells comprise at least one PLA memory cell.
16. The method of claim 11 comprising precharging and equalizing at least one line coupled to at least one of said self-timed local sense amplifier, said local decoder and said cell array.
17. The method of claim 9 comprising interfacing at least one self-timed local controller with a self-timed local decoder and a self-timed sense amplifier.
18. The method of claim 17 comprising coordinating said self-timed local decoder and said self-timed sense amplifier using said self-timed local controller.
19. A method of forming a synchronous controlled hierarchical memory structure, the method comprising:
forming at least one cell array having a plurality of memory cells;
interfacing at least one self-timed local decoder with said at least one cell array;
interfacing at least one self-timed local sense amplifier with at least said at least one self-timed local decoder and said at least one cell array;
interfacing at least one self-timed local controller with at least said at least one self-timed local decoder and said at least one self-timed local sense amplifier; and
precharging and equalizing at least one line coupled to at least one of said self-timed local sense amplifier, said self-timed local decoder and said cell array using said at least one self-timed local sense amplifier.
20. The method of claim 19 comprising coordinating said at least one self-timed local decoder and said at least one self-timed local sense amplifier using said at least one self-timed local controller.
21. The method of claim 20 comprising interfacing at least one synchronously controlled global element with at least one of said cell array, said self-timed local decoder and said self-timed local sense amplifier.
22. The method of claim 21 , wherein said at least one synchronously controlled global element comprises at least one of a global predecoder, a global decoder, a global controller and a global sense amplifier.
23. A method of forming a synchronous controlled hierarchical memory structure that comprises a logical portion of a larger memory device, the method comprising:
forming at least one cell array having a plurality of memory cells;
interfacing at least one self-timed local decoder with said at least one cell array;
interfacing at least one self-timed local sense amplifier with said at least one self-timed local decoder and said at least one cell array;
precharging and equalizing at least one line coupled thereto;
interfacing at least one self-timed local controller with said at least one self-timed local decoder and said at least one self-timed local sense amplifier;
coordinating said at least one self-timed local decoder and said at least one self-timed local sense amplifier; and
interfacing at least one synchronously controlled global element with at least one of said cell array, said self-timed local controller, said self-timed local decoder and said self-timed local sense amplifier.
24. The method of claim 23 , wherein said at least one synchronously controlled global element comprises at least one of a global predecoder, a global decoder, a global controller and a global sense amplifier.