IP Library › Granted Patent US 12,557,415
Granted Patent B2
US 12,557,415 · App. 17/998,990 · Granted Feb 17, 2026

Imaging element and imaging device

Inventors: Ryoto Yoshita (Kanagawa, JP); Yoshimichi Kumagai (Kanagawa, JP); Naoyuki Osawa (Kanagawa, JP); Kengo Nagata (Kanagawa, JP); Masashi Bando (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H10F39/8067H10F39/18H10F39/8057H10F39/8063H10F39/811
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Quick Facts
Patent No.
US 12,557,415
App. No.
17/998,990
Granted
Feb 17, 2026
Kind
B2
Abstract

An imaging element is disclosed that includes: a semiconductor substrate; a multilayer wiring layer; a plurality of structures; and a light reflecting layer. The semiconductor substrate has a first surface as a light incidence surface and a second surface opposite to the first surface. A light receiving section of the semiconductor substrate generates electric charge through photoelectric conversion. The multilayer wiring layer has a plurality of wiring layers and is on the second surface side of the semiconductor substrate. The plurality of structures is in the multilayer wiring layer. The light reflecting layer is in the multilayer wiring layer, and forms a reflective region or a non-reflective region in a region with the interlayer insulating layer interposed in between. The region has none of the structures formed therein. The reflective region and the non-reflective region are substantially symmetrical with respect to the optical center of the pixel.

Claims (62)

1 . An imaging element, comprising:

a semiconductor substrate having a first surface and a second surface, the first surface serving as a light incidence surface, the second surface being opposite to the first surface, the semiconductor substrate including a light receiving section for each pixel included in a plurality of pixels, the light receiving section generating electric charge through photoelectric conversion, the electric charge corresponding to an amount of received light;

a multilayer wiring layer that is provided on a second surface side of the semiconductor substrate, the multilayer wiring layer having a plurality of wiring layers stacked therein with an interlayer insulating layer interposed in between;

a plurality of structures that is provided on the second surface of the semiconductor substrate in the multilayer wiring layer; and

a light reflecting layer that is provided in the multilayer wiring layer,

wherein the light reflecting layer forms a reflective region and a non-reflective region in a region with the interlayer insulating layer interposed in between,

wherein the region has none of the structures formed therein,

wherein the reflective region is substantially symmetrical with respect to an optical center of each pixel included in the plurality of pixels,

wherein the non-reflective region is substantially symmetrical with respect to the optical center of each pixel included in the plurality of pixels,

wherein, in each pixel included in the plurality of pixels, the reflective region surrounds the non-reflective region, and

wherein the light reflecting layer includes an uneven structure on a surface opposed to the second surface of the semiconductor substrate.

2 . The imaging element according to claim 1 , wherein the light reflecting layer is formed to be substantially symmetrical with respect to the optical center of each pixel included in the plurality of pixels.

3 . The imaging element according to claim 1 , wherein the light reflecting layer has an opening.

4 . The imaging element according to claim 3 , wherein the opening is formed to be substantially symmetrical, the opening including the optical center of the pixel.

5 . The imaging element according to claim 1 , wherein the plurality of structures is disposed to be asymmetrical in the pixel in a plan view.

6 . The imaging element according to claim 1 , further comprising:

a first pixel and a second pixel as the pixels, the first pixel and the second pixel being adjacent to each other, wherein

the light reflecting layer is formed to be substantially symmetrical by using a region between the first pixel and the second pixel as a center.

7 . The imaging element according to claim 6 , wherein a portion of a plurality of structures is shared between the first pixel and the second pixel.

8 . The imaging element according to claim 1 , wherein the light reflecting layer is provided to overlap with a portion of the plurality of structures in a plan view.

9 . The imaging element according to claim 1 , wherein the plurality of structures includes a floating diffusion, a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor, the floating diffusion performing electric charge voltage conversion to convert signal charge generated by the light receiving section into a voltage signal, the transfer transistor transferring the signal charge generated by the light receiving section to the floating diffusion, the reset transistor resetting a potential of the floating diffusion to a predetermined potential, the amplification transistor serving an input section of the voltage signal held by the floating diffusion, the selection transistor controlling an output timing of the voltage signal from the amplification transistor.

10 . The imaging element according to claim 8 , further comprising an electric charge holding section that is provided for each of the pixels as the plurality of structures, the electric charge holding section accumulating the electric charge generated by the light receiving section.

11 . The imaging element according to claim 1 , wherein the uneven structure has a shape that is substantially symmetrical with respect to the optical center.

12 . The imaging element according to claim 1 , further comprising a pixel section in which the pixels included in the plurality of pixels are two two-dimensionally disposed in a matrix, wherein

light reflecting layers provided in the plurality of pixels included in the pixel section are formed to cause at least one of the reflective regions or the non-reflective regions to shift from the optical centers of the plurality of pixels as viewed from a middle of the pixel section toward a peripheral portion.

13 . An imaging element, comprising:

a semiconductor substrate having a first surface and a second surface, the first surface serving as a light incidence surface, the second surface being opposite to the first surface, the semiconductor substrate including a light receiving section for each pixel included in a plurality of pixels, the light receiving section generating electric charge through photoelectric conversion, the electric charge corresponding to an amount of received light;

a multilayer wiring layer that is provided on a second surface side of the semiconductor substrate, the multilayer wiring layer having a plurality of wiring layers stacked therein with an interlayer insulating layer interposed in between;

a plurality of structures that is provided on the second surface of the semiconductor substrate in the multilayer wiring layer;

a light reflecting layer that is provided in the multilayer wiring layer,

wherein the light reflecting layer forms a reflective region and a non-reflective region in a region with the interlayer insulating layer interposed in between,

wherein the region has none of the structures formed therein,

wherein the reflective region is substantially symmetrical with respect to an optical center of each pixel included in the plurality of pixels,

wherein the non-reflective region is substantially symmetrical with respect to the optical center of each pixel in the plurality of pixels; and

a light reflection control layer above the second surface of the semiconductor substrate, the light reflection control layer having different refractive indexes in a plane.

14 . The imaging element according to claim 13 , wherein the light reflection control layer is formed by using metamaterials having different refractive indexes from each other.

15 . The imaging element according to claim 13 , wherein the light reflecting layer includes a meta-lens.

16 . The imaging element according to claim 13 , wherein the light reflecting layer includes an uneven structure on a surface opposed to the second surface of the semiconductor substrate.

17 . An imaging element, comprising:

a semiconductor substrate having a first surface and a second surface, the first surface serving as a light incidence surface, the second surface being opposite to the first surface, the semiconductor substrate including a light receiving section for each pixel included in a plurality of pixels, the light receiving section generating electric charge through photoelectric conversion, the electric charge corresponding to an amount of received light;

a multilayer wiring layer that is provided on a second surface side of the semiconductor substrate, the multilayer wiring layer having a plurality of wiring layers stacked therein with an interlayer insulating layer interposed in between;

a plurality of structures that is provided on the second surface of the semiconductor substrate in the multilayer wiring layer; and

a light reflecting layer that is provided in the multilayer wiring layer,

wherein the light reflecting layer forms a reflective region and a non-reflective region in a region with the interlayer insulating layer interposed in between,

wherein the region has none of the structures formed therein,

wherein the reflective region is substantially symmetrical with respect to an optical center of each pixel included in the plurality of pixels,

wherein the non-reflective region is substantially symmetrical with respect to the optical center of each pixel included in the plurality of pixels,

wherein, in each pixel included in the plurality of pixels, the reflective region surrounds the non-reflective region, and

wherein the semiconductor substrate includes an uneven structure on the second surface.

18 . The imaging element according to claim 17 , wherein the semiconductor substrate has a curved section as the uneven structure, the curved section being substantially symmetrical with respect the optical center.

19 . The imaging element according to claim 17 , wherein a reflective film is formed on a surface of the uneven structure.

20 . An imaging element, comprising:

a semiconductor substrate having a first surface and a second surface, the first surface serving as a light incidence surface, the second surface being opposite to the first surface, the semiconductor substrate including a light receiving section for each pixel included in a plurality of pixels, the light receiving section generating electric charge through photoelectric conversion, the electric charge corresponding to an amount of received light;

a multilayer wiring layer that is provided on a second surface side of the semiconductor substrate, the multilayer wiring layer having a plurality of wiring layers stacked therein with an interlayer insulating layer interposed in between;

a plurality of structures that is provided on the second surface of the semiconductor substrate in the multilayer wiring layer; and

a light reflecting layer that is provided in the multilayer wiring layer,

wherein the light reflecting layer forms a reflective region and a non-reflective region in a region with the interlayer insulating layer interposed in between,

wherein the region has none of the structures formed therein,

wherein the reflective region is substantially symmetrical with respect to an optical center of each pixel included in the plurality of pixels,

wherein the non-reflective region is substantially symmetrical with respect to the optical center of each pixel included in the plurality of pixels,

wherein, in each pixel included in the plurality of pixels, the reflective region surrounds the non-reflective region, and

wherein the plurality of structures is disposed to be asymmetrical in the pixel in a plan view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2022
From: YOSHITA, RYOTO; KUMAGAI, YOSHIMICHI; OSAWA, NAOYUKI; NAGATA, KENGO; BANDO, MASASHI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 061794/0347 →
Priority Claims (1)
JP 2020-095062 · May 29, 2020 · national
Continuity (1)
Related Publication 20230215889A1 · Jul 6, 2023
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