IP Library › Granted Patent US 12,563,895
Granted Patent B2
US 12,563,895 · App. 18/037,371 · Granted Feb 24, 2026

Method for manufacturing display apparatus, display apparatus, display module, and electronic device

Inventors: Shunpei Yamazaki (Setagaya, JP); Shingo Eguchi (Atsugi, JP); Tomoya Aoyama (Atsugi, JP); Daiki Nakamura (Atsugi, JP); Kenichi Okazaki (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10K59/1201H10K59/873H10K71/231
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Quick Facts
Patent No.
US 12,563,895
App. No.
18/037,371
Granted
Feb 24, 2026
Kind
B2
Abstract

A high-resolution, high-definition, or large display apparatus is provided. A metal mask is placed over an EL layer and film deposition is performed with the metal mask, whereby an island-shaped counter electrode is formed. Then, the EL layer is processed using the counter electrode as a hard mask. Alternatively, after an EL layer and a counter electrode are formed over an entire surface, processing using a metal mask is performed. An insulating layer that electrically insulates adjacent pixel electrodes from each other is positioned between adjacent light-emitting devices. A resist mask is formed over the insulating layer. A plurality of EL layers and a plurality of counter electrodes overlapping each other over the insulating layer are partly removed using the resist mask, whereby part of the insulating layer is exposed. Thus, the adjacent light-emitting devices are electrically insulated from each other over the insulating layer.

Claims (50)

1 . A method for manufacturing a display apparatus, comprising:

forming a first pixel electrode and a second pixel electrode;

forming an insulating layer covering an end portion of the first pixel electrode and an end portion of the second pixel electrode;

forming a first layer over the first pixel electrode, the second pixel electrode, and the insulating layer;

placing a first metal mask comprising a first opening over the first layer so that the first opening overlaps the first pixel electrode;

forming a first counter electrode overlapping the first pixel electrode with the first layer therebetween by performing film deposition with the first metal mask;

removing at least part of a region overlapping the second pixel electrode of the first layer using the first counter electrode as a hard mask;

forming a second layer over the first pixel electrode, the second pixel electrode, and the insulating layer;

placing a second metal mask comprising a second opening over the second layer so that the second opening overlaps the second pixel electrode;

forming a second counter electrode overlapping the second pixel electrode with the second layer therebetween by performing film deposition with the second metal mask;

removing at least part of a region overlapping the first pixel electrode of the second layer using the second counter electrode as a hard mask;

forming, over the first counter electrode and the second counter electrode, a resist mask comprising an opening at a position overlapping the insulating layer;

exposing part of the insulating layer by removing at least part of a region overlapping the insulating layer of at least one of the first layer, the second layer, the first counter electrode, and the second counter electrode using the resist mask; and

forming a first protective layer covering the first counter electrode, the second counter electrode, and the insulating layer.

2 . The method for manufacturing a display apparatus according to claim 1 , further comprising:

before the formation of the first counter electrode, forming a second protective layer overlapping the first pixel electrode with the first layer therebetween by performing film deposition with the first metal mask; and

before the formation of the second counter electrode, forming a third protective layer overlapping the second pixel electrode with the second layer therebetween by performing film deposition with the second metal mask.

3 . The method for manufacturing a display apparatus according to claim 2 ,

wherein a thickness of the second protective layer and a thickness of the third protective layer are different from each other.

4 . The method for manufacturing a display apparatus according to claim 2 ,

wherein at least one of a metal oxide layer comprising indium, gallium, and zinc and a metal oxide layer comprising indium and tin is formed as each of the second protective layer and the third protective layer.

5 . The method for manufacturing a display apparatus according to claim 1 , further comprising:

after the formation of the first counter electrode, forming a fourth protective layer overlapping the first pixel electrode with the first counter electrode therebetween by performing film deposition with the first metal mask.

6 . The method for manufacturing a display apparatus according to claim 5 ,

wherein at least one of a metal oxide layer comprising indium, gallium, and zinc and a metal oxide layer comprising indium and tin is formed as the fourth protective layer.

7 . A method for manufacturing a display apparatus, comprising:

forming a first pixel electrode and a second pixel electrode;

forming an insulating layer covering an end portion of the first pixel electrode and an end portion of the second pixel electrode;

forming a first layer over the first pixel electrode, the second pixel electrode, and the insulating layer;

forming a first counter electrode over the first layer;

placing a first metal mask comprising a first opening over the first counter electrode so that the first opening overlaps the second pixel electrode;

removing at least part of a region overlapping the second pixel electrode of the first layer and the first counter electrode using the first metal mask;

forming a second layer over the first pixel electrode, the second pixel electrode, and the insulating layer;

forming a second counter electrode over the second layer;

placing a second metal mask comprising a second opening over the second counter electrode so that the second opening overlaps the first pixel electrode;

removing at least part of a region overlapping the first pixel electrode of the second layer and the second counter electrode using the second metal mask;

forming, over the first counter electrode and the second counter electrode, a resist mask comprising an opening at a position overlapping the insulating layer;

exposing part of the insulating layer by removing at least part of a region overlapping the insulating layer of at least one of the first layer, the second layer, the first counter electrode, and the second counter electrode using the resist mask; and

forming a first protective layer covering the first counter electrode, the second counter electrode, and the insulating layer.

8 . The method for manufacturing a display apparatus according to claim 7 , further comprising:

forming a second protective layer over the first layer before the formation of the first counter electrode; and

forming a third protective layer over the second layer before the formation of the second counter electrode.

9 . The method for manufacturing a display apparatus according to claim 8 ,

wherein a thickness of the second protective layer and a thickness of the third protective layer are different from each other.

10 . The method for manufacturing a display apparatus according to claim 8 ,

wherein at least one of a metal oxide layer comprising indium, gallium, and zinc and a metal oxide layer comprising indium and tin is formed as each of the second protective layer and the third protective layer.

11 . The method for manufacturing a display apparatus according to claim 7 , further comprising:

forming a fourth protective layer over the first counter electrode before the placement of the first metal mask.

12 . The method for manufacturing a display apparatus according to claim 11 ,

wherein at least one of a metal oxide layer comprising indium, gallium, and zinc and a metal oxide layer comprising indium and tin is formed as the fourth protective layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2023
From: YAMAZAKI, SHUNPEI; EGUCHI, SHINGO; AOYAMA, TOMOYA; NAKAMURA, DAIKI; OKAZAKI, KENICHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 063671/0564 →
Priority Claims (1)
JP 2020-202379 · Dec 7, 2020 · national
Continuity (1)
Related Publication 20230420614A1 · Dec 28, 2023
References Cited (69)
US 5953985A · Kobayashi · 1999 [cited by applicant]
US 6120338A · Hirano et al. · 2000 [cited by applicant]
US 6146715A · Kim et al. · 2000 [cited by applicant]
US 10608064B2 · Lee · 2020 [cited by examiner]
US 11678550B2 · Kato · 2023 [cited by applicant]
US 20020072139A1 · Kashiwabara · 2002 [cited by applicant]
US 20090179210A1 · Cok · 2009 [cited by examiner]
US 20110148290A1 · Oota · 2011 [cited by applicant]
US 20120256204A1 · Yoshizumi et al. · 2012 [cited by applicant]
US 20120273804A1 · Hatano · 2012 [cited by applicant]
US 20120276484A1 · Izumi et al. · 2012 [cited by applicant]
US 20130084531A1 · Hamaguchi et al. · 2013 [cited by applicant]
US 20130084664A1 · Yoshitoku et al. · 2013 [cited by applicant]
US 20130084666A1 · Oshige · 2013 [cited by applicant]
US 20130280839A1 · Sonoda et al. · 2013 [cited by applicant]
US 20130295705A1 · Sonoda et al. · 2013 [cited by applicant]
US 20140004640A1 · Hamaguchi et al. · 2014 [cited by applicant]
US 20140004642A1 · Otsuka et al. · 2014 [cited by applicant]
US 20150060826A1 · Matsumoto et al. · 2015 [cited by applicant]
US 20150069360A1 · Sato · 2015 [cited by applicant]
US 20150076476A1 · Odaka et al. · 2015 [cited by applicant]
US 20160172595A1 · Malinowski et al. · 2016 [cited by applicant]
US 20160315133A1 · Sato · 2016 [cited by applicant]
US 20170141167A1 · Naganuma · 2017 [cited by applicant]
US 20170256754A1 · Defranco et al. · 2017 [cited by applicant]
US 20180190908A1 · Ke et al. · 2018 [cited by applicant]
US 20180261792A1 · Kwon et al. · 2018 [cited by applicant]
US 20200057330A1 · Yamazaki et al. · 2020 [cited by applicant]
US 20200203662A1 · Mollard et al. · 2020 [cited by applicant]
US 20210265432A1 · Kato · 2021 [cited by applicant]
US 20220130918A1 · Yamazaki et al. · 2022 [cited by applicant]
CN 001239395A · 1999 [cited by applicant]
CN 108574057A · 2018 [cited by applicant]
CN 109509765A · 2019 [cited by applicant]
CN 112314056A · 2021 [cited by applicant]
EP 0966182A · 1999 [cited by applicant]
JP 2000012220A · 2000 [cited by applicant]
JP 2000036385A · 2000 [cited by applicant]
JP 2000113982A · 2000 [cited by applicant]
JP 2003059663A · 2003 [cited by applicant]
JP 2003347053A · 2003 [cited by applicant]
JP 2008098106A · 2008 [cited by applicant]
JP 2008147072A · 2008 [cited by applicant]
JP 2008251270A · 2008 [cited by applicant]
JP 2010008317A · 2010 [cited by applicant]
JP 2014120218A · 2014 [cited by applicant]
JP 2014135251A · 2014 [cited by applicant]
JP 2014232568A · 2014 [cited by applicant]
JP 2015115178A · 2015 [cited by applicant]
JP 2016197494A · 2016 [cited by applicant]
JP 2019179696A · 2019 [cited by applicant]
JP 2020160305A · 2020 [cited by applicant]
KR 20000002154A · 2000 [cited by applicant]
KR 20180104227A · 2018 [cited by applicant]
WO WO2018087625 · 2018 [cited by applicant]
WO WO2020004086 · 2020 [cited by applicant]
Zakhidov.A et al., “Orthogonal processing: A new strategy for organic electronics”, Chem. Sci. (Chemical Science), Apr. 7, 2011, vol. 2, No. 6, pp. 1178-1182. [cited by applicant]
Malinowski.P et al., “High resolution photolithography for direct view active matrix organic light-emitting diode augmented reality displays”, J. Soc. Inf. Display (Journal of the Society for Information Display), Apr. … [cited by applicant]
Malinowski.P et al., “Photolithographic patterning of organic photodetectors with a non-fluorinated photoresist system”, Organic Electronics, Jul. 12, 2014, vol. 15, No. 10, pp. 2355-2359. [cited by applicant]
Malinowski.P et al., “Multicolor 1250 ppi OLED Arrays Patterened by Photolithography”, SID Digest '16 : SID International Symposium Digest of Technical Papers, May 22, 2016, vol. 47, No. 1, pp. 1009-1012. [cited by applicant]
Papadopoulos.N et al., “AMOLED Displays with In-Pixel Photodetector”, Liquid Crystals and Display Technology, Jul. 9, 2020, pp. 1-19. [cited by applicant]
Ke.T et al., “Technology Developments in High-Resolution FMM-free OLED and BEOL IGZO TFTs for Power-Efficient Microdisplays”, SID Digest '21 : SID International Symposium Digest of Technical Papers, May 1, 2021, vol. 52… [cited by applicant]
Malinowski.P et al., “Integration of additional functionalities into the frontplane of AMOLED displays”, SID Digest '20 : SID International Symposium Digest of Technical Papers, Aug. 1, 2020, vol. 51, No. 1, pp. 646-649. [cited by applicant]
Malinowski.P et al., “Organic photolithography for displays with integrated fingerprint scanner”, SID Digest '19 : SID International Symposium Digest of Technical Papers, May 29, 2019, vol. 50, No. 1, pp. 1007-1010. [cited by applicant]
Ke. T et al., “Island and Hole Fabrication on OLED Stack for High-Resolution Sensor in Display Application”, IDW '20 : Proceedings of the 27th International Display Workshops, Dec. 9, 2020, vol. 27, pp. 902-905. [cited by applicant]
Gather.M et al., “Solution-Processed Full-Color Polymer-OLED Displays Fabricated by Direct Photolithography”, SID Digest '06 : SID International Symposium Digest of Technical Papers, Jun. 1, 2006, vol. 37, No. 1, pp. 90… [cited by applicant]
Malinowski.P et al., “Photolithography as Enabler of AMOLED Displays Beyond 1000 ppi”, SID Digest '17 : SID International Symposium Digest of Technical Papers, May 1, 2017, vol. 48, No. 1, pp. 623-626. [cited by applicant]
International Search Report (Application No. PCT/IB2021/060952) dated Mar. 22, 2022. [cited by applicant]
Written Opinion (Application No. PCT/IB2021/060952) dated Mar. 22, 2022. [cited by applicant]