Memory device
A memory device is provided. The memory device includes a first structure and a second structure stacked on the first structure in a vertical direction. The first structure includes a first substrate, peripheral circuitry, an auxiliary memory cell array, a first insulating layer, and a plurality of first bonding pads. The second structure includes a second substrate, a main memory cell array, a second insulating layer, and a plurality of second bonding pads. The plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively.
1 . A memory device comprising:
a first structure and a second structure stacked on the first structure in a vertical direction,
wherein the first structure comprises:
a first substrate;
peripheral circuitry on the first substrate;
an auxiliary memory cell array on the first substrate;
a first insulating layer on the first substrate, the peripheral circuitry, and the auxiliary memory cell array; and
a plurality of first bonding pads on the first insulating layer and electrically connected to the peripheral circuitry, and
the second structure comprises:
a second substrate;
a main memory cell array on the second substrate;
a second insulating layer on the second substrate and the main memory cell array; and
a plurality of second bonding pads on the second insulating layer and electrically connected to the main memory cell array,
wherein the plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively, and
wherein one or more dimensions of the auxiliary memory cell array are smaller than those of the main memory cell array.
2 . The memory device of claim 1 , wherein a planar area of the auxiliary memory cell array perpendicular to the vertical direction is less than a planar area of the main memory cell array perpendicular to the vertical direction.
3 . The memory device of claim 1 , wherein a volume of the auxiliary memory cell array is less than a volume of the main memory cell array.
4 . The memory device of claim 1 , wherein:
the auxiliary memory cell array comprises a first stack structure on the first substrate and a plurality of first channel structures extending through the first stack structure in the vertical direction, the first stack structure comprising first interlayer insulating layers and first gate layers alternately stacked with each other on the first substrate; and
the main memory cell array comprises a second stack structure on the second substrate and a plurality of second channel structures extending through the second stack structure in the vertical direction, the second stack structure comprising second interlayer insulating layers and second gate layers alternately stacked with each other on the second substrate.
5 . The memory device of claim 4 , wherein a number of the first gate layers in the first stack structure is fewer than a number of the second gate layers in the second stack structure.
6 . The memory device of claim 1 , wherein the auxiliary memory cell array is configured to provide additional storage capacity in addition to a storage capacity of the main memory cell array.
7 . The memory device of claim 1 , wherein the auxiliary memory cell array is configured to repair the main memory cell array.
8 . A memory device comprising:
a first structure and a second structure stacked on the first structure in a vertical direction,
wherein the first structure comprises:
a first substrate;
peripheral circuitry on the first substrate;
at least one auxiliary memory cell array on the first substrate;
a first insulating layer on the first substrate, the peripheral circuitry, and the at least one auxiliary memory cell array; and
a plurality of first bonding pads on the first insulating layer and electrically connected to the peripheral circuitry, and
the second structure comprises:
a second substrate;
a plurality of main memory cell arrays on the second substrate;
a second insulating layer on the second substrate and the plurality of main memory cell arrays; and
a plurality of second bonding pads on the second insulating layer and electrically connected to the plurality of main memory cell arrays, wherein
the plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively, and
a number of the at least one auxiliary memory cell array is fewer than a number of the main memory cell arrays.
9 . The memory device of claim 8 , wherein a planar area of each of the at least one auxiliary memory cell array perpendicular to the vertical direction is equal to a planar area of each of the plurality of main memory cell arrays perpendicular to the vertical direction.
10 . The memory device of claim 8 , wherein a planar area of each of the at least one auxiliary memory cell array perpendicular to the vertical direction is less than a planar area of each of the plurality of main memory cell arrays perpendicular to the vertical direction.
11 . The memory device of claim 8 , wherein a number of memory cells in each of the at least one auxiliary memory cell array is fewer than or equal to a number of memory cells in each of the plurality of main memory cell arrays.
12 . The memory device of claim 8 , wherein the at least one auxiliary memory cell array is laterally adjacent the peripheral circuitry on the first substrate.
13 . The memory device of claim 8 , wherein:
each of the at least one auxiliary memory cell array comprises a first stack structure on the first substrate and a plurality of first channel structures extending through the first stack structure in the vertical direction, the first stack structure comprising first interlayer insulating layers and first gate layers alternately stacked with each other on the first substrate; and
each of the plurality of main memory cell arrays comprises a second stack structure on the second substrate and a plurality of second channel structures extending through the second stack structure in the vertical direction, the second stack structure comprising second interlayer insulating layers and second gate layers alternately stacked with each other on the second substrate.
14 . The memory device of claim 13 , wherein a number of the first gate layers in the first stack structure is equal to a number of the second gate layers in the second stack structure.
15 . The memory device of claim 13 , wherein a number of the first gate layers in the first stack structure is fewer than a number of the second gate layers in the second stack structure.
16 . The memory device of claim 8 , wherein the at least one auxiliary memory cell array is configured to provide additional storage capacity in addition to a storage capacity of the plurality of main memory cell arrays.
17 . The memory device of claim 8 , wherein the at least one auxiliary memory cell array is configured to repair the plurality of main memory cell arrays.
18 . A memory device comprising:
a first structure and a second structure stacked on the first structure in a vertical direction,
wherein the first structure comprises:
a first substrate;
peripheral circuitry on the first substrate;
a first insulating layer on the first substrate and the peripheral circuitry;
a second substrate on the first insulating layer;
an auxiliary memory cell array on the second substrate;
a second insulating layer on the second substrate and the auxiliary memory cell array; and
a plurality of first bonding pads on the second insulating layer and electrically connected to the peripheral circuitry, and
the second structure comprises:
a third substrate;
a main memory cell array on the third substrate;
a third insulating layer on the third substrate and the main memory cell array; and
a plurality of second bonding pads on the third insulating layer and electrically connected to the main memory cell array,
wherein the plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively, and
wherein one or more dimensions of the auxiliary memory cell array are smaller than those of the main memory cell array.
19 . The memory device of claim 18 , wherein a volume of the auxiliary memory cell array is less than a volume of the main memory cell array.
20 . The memory device of claim 18 , wherein:
the auxiliary memory cell array comprises a first stack structure on the second substrate and a plurality of first channel structures extending through the first stack structure in the vertical direction, the first stack structure comprising first interlayer insulating layers and first gate layers alternately stacked with each other on the second substrate,
the main memory cell array comprises a second stack structure on the third substrate and a plurality of second channel structures extending through the second stack structure in the vertical direction, the second stack structure comprising second interlayer insulating layers and second gate layers alternately stacked with each other on the third substrate, and
a number of the first gate layers in the first stack structure is less than a number of the second gate layers in the second stack structure.