Trench etching process for photoresist line roughness improvement

1. A method of forming a semiconductor device structure, comprising:

forming a resist structure over a hard mask, the resist structure comprising an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer;

patterning the photoresist layer to form a trench therein;

performing a hydrogen plasma treatment to the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth sidewalls of the trench, and the hydrogen plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C.;

patterning the hard mask using the patterned photoresist layer as a etch mask;

forming another resist structure over the hard mask, the another resist structure comprising another anti-reflective coating (ARC) layer and another photoresist layer over the another ARC layer;

patterning the another photoresist layer to form another trench therein;

performing another hydrogen plasma treatment to the patterned another photoresist layer; and

patterning the hard mask using the patterned another photoresist layer as a second etch mask.

2. The method of claim 1 , wherein performing the hydrogen plasma treatment comprises using a process gas comprising a hydrogen gas and a carrier gas.

3. The method of claim 1 , wherein performing the hydrogen plasma treatment comprises reducing a line edge roughness (LER) of the sidewalls to a LER ranging from 3.8 nanometers (nm) to 4.8 nm.

4. The method of claim 2 , wherein performing the hydrogen plasma treatment comprises supplying the hydrogen gas at a flow rate ranging from about 20 standard cubic centimeters per minute (sccm) to about 500 sccm.

5. The method of claim 2 , wherein performing the hydrogen plasma treatment comprises supplying the carrier gas at a flow rate ranging from about 10 sccm to about 300 sccm.

6. The method of claim 2 , wherein the process gas further comprises fluoromethane (CH 3 F), difluoromethane (CH 2 F 2 ), or trifluoromethane (CHF 3 ).

7. The method of claim 1 , wherein forming the resist structure further comprises:

forming an organic planarization layer (OPL), wherein the ARC layer is over the OPL; and

patterning the OPL using the patterned photoresist layer as an etch mask.

8. The method of claim 1 , wherein the another hydrogen plasma treatment is configured to smooth sidewalls of the another trench without etching the another ARC layer; and

patterning the another ARC layer using the patterned another photoresist layer as a etch mask.

9. A method of forming a semiconductor device structure, comprising:

forming a first photoresist layer over a hard mask, wherein the hard mask is over a substrate;

patterning the first photoresist layer to form a first pattern comprising a plurality of first trenches therein;

performing a first hydrogen plasma treatment to the patterned first photoresist layer, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the plurality of first trenches;

transferring the first pattern into the hard mask to form a plurality of second trenches in the hard mask;

forming a second resist structure over the patterned hard mask layer and in the plurality of second trenches;

patterning the second photoresist layer to form a second pattern comprising a plurality of third trenches therein;

performing a second hydrogen plasma treatment to the patterned second photoresist layer, wherein the second hydrogen plasma treatment is configured to smooth sidewalls of the plurality of third trenches; and

transferring the second pattern into the patterned hard mask layer to form a plurality of fourth trenches in the patterned hard mask layer, wherein each of the plurality of fourth trenches is disposed between two adjacent second trenches of the plurality of second trenches.

10. The method of claim 9 , wherein the second hydrogen plasma treatment has at least one different parameter from the first hydrogen plasma treatment.

11. The method of claim 9 , further comprising:

forming an interlayer dielectric (ILD) over the substrate, wherein the hard mask is over the ILD;

patterning the ILD layer using the patterned hard mask layer as an etch mask.

12. The method of claim 9 , further comprising:

forming a first resist structure over the hard mask, wherein the first resist structure comprises an organic planarization layer (OPL), an anti-reflective coating (ARC) layer over the OPL, and the first photoresist layer over the ARC layer.

13. The method of claim 9 , further comprising:

forming a second resist structure over the hard mask, wherein the second resist structure comprises an organic planarization layer (OPL), an anti-reflective coating (ARC) layer over the first OPL, and the second photoresist layer over the ARC layer.

14. The method of claim 9 , wherein performing the second hydrogen plasma treatment comprises performing the second hydrogen plasma treatment at a temperature ranging from about 200° C. to about 600° C.

15. The method of claim 9 , wherein performing the second hydrogen plasma treatment comprises introducing a fluorine-containing gas.

16. A method of forming a semiconductor device structure, comprising:

forming a resist structure over a hard mask, the resist structure comprising an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer;

patterning the photoresist layer to form a trench therein;

performing a plasma treatment to the patterned photoresist layer, wherein the plasma treatment is configured to smooth sidewalls of the trench, the plasma treatment comprises introducing a hydrogen-containing gas and a fluorine-containing gas, and the plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C.;

patterning the hard mask using the patterned photoresist layer as a first etch mask;

forming a second resist structure over the hard mask, the resist structure comprising an a second photoresist layer;

patterning the second photoresist layer to form a second trench therein; and

performing a second plasma treatment on the pattern photoresist layer, wherein the second plasma treatment comprises introducing the hydrogen-containing gas; and

patterning the hard mask using the patterned second photoresist layer as a second etch mask.

17. The method of claim 16 , wherein performing the plasma treatment comprises reducing a line edge roughness (LER) of the trench to 3.8 nanometers (nm) to 4.8 nm.

18. The method of claim 17 , wherein patterning the photoresist layer comprises defining the trench having an LER of 7 nm to 8 nm.

19. The method of claim 16 , further comprising forming an opening in a dielectric layer using the patterned hard mask.

20. The method of claim 19 , further comprising depositing a conductive material in the opening.