Hardware-based power management integrated circuit register file write protection
View Patent ↗Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.
1 . A device comprising:
a register file including one or more registers, wherein a first register of the one or more registers includes a pre-configured bit hardwired to a control input of the register file and a plurality of remaining bits storing data, and further includes a write-enable port, the pre-configured bit hard-wired to the write-enable port; and
a controller coupled with the register file and configured to:
enable a write mode of the register file in response to an enablement signal located at a position of the pre-configured bit, wherein the enablement signal comprises a bit string identifying the first register and the position of the pre-configured bit;
write, after enabling the write mode, data to a second register of the register file;
receive, based at least in part on writing the data to the second register, a disablement signal identifying the first register and the position of the pre-configured bit of the first register; and
enable a write protection mode of the register file by re-setting the pre-configured bit of the first register in accordance with the disablement signal, wherein the write mode is disabled by enabling the write protection mode.
2 . The device of claim 1 , wherein the pre-configured bit comprises a write register bit (WRB) located at the position of the pre-configured bit and wherein remaining bits, other than the pre-configured bit, store user data.
3 . The device of claim 1 , further comprising one or more switch drivers, voltage regulators and a sequencer, the one or more switch drivers, the voltage regulators and the sequencer controlled by values stored in the register file.
4 . The device of claim 1 , wherein the controller is further configured to receive a second write request, the second write request toggling a value of the pre-configured bit.
5 . The device of claim 4 , wherein receiving the second write request comprises receiving a stop bit immediately after writing a first message to the register file.
6 . The device of claim 1 , wherein receiving a second write request comprises receiving a stop bit after writing multiple messages to the register file.
7 . The device of claim 1 , the first register comprising data encoded using a linear block code.
8 . A method comprising:
receiving an enablement signal, via an interface configured to receive messages from a host application, the messages including the enablement signal, the enablement signal identifying a first register and a pre-configured bit of the first register, the first register having a plurality of remaining bits storing data, wherein the enablement signal comprises a bit string identifying the first register and a position of the pre-configured bit;
enabling a write mode of a register file by setting the pre-configured bit of the first register in accordance with the enablement signal, the pre-configured bit hardwired to a control input of the register file;
writing, after enabling the write mode, data to a second register of the register file;
receiving, via the interface and based at least in part on writing the data to the second register, a disablement signal identifying the first register and the position of the pre-configured bit of the first register; and
enabling a write protection mode of the register file by re-setting the pre-configured bit of the first register in accordance with the disablement signal, wherein the write mode is disabled by enabling the write protection mode.
9 . The method of claim 8 , further comprising initializing the pre-configured bit upon startup.
10 . The method of claim 8 , wherein enabling the write mode comprises enabling a first or last bit of the first register.
11 . The method of claim 8 , wherein receiving the enablement signal comprises receiving the enablement signal over an I2C bus.
12 . The method of claim 8 , further comprising receiving a stop bit immediately after writing a first message to the register file.
13 . The method of claim 12 , wherein receiving the stop bit over comprises receiving the stop bit after writing multiple messages to the register file.
14 . The method of claim 8 , further comprising:
receiving a second write request;
determining if the register file is in the write mode; and
selectively ignoring the second write request if the register file is not in the write mode.
15 . The method of claim 14 , wherein selectively ignoring further comprises setting a counter to disable further write requests for a predefined number of clock cycles.