IP Library Granted Patent US 12,193,142
Granted Patent B2
US 12,193,142 · App. 18/063,136 · Granted Jan 7, 2025

Ground discontinuities for thermal isolation

Inventors: Trevor Timpane (Rochester, MN); Layne A. Berge (Rochester, MN); Patryk Gumann (Tarrytown, NY); Sean Hart (Tarrytown, NY); Curtis Eugene Larsen (Eden Valley, MN); Michael Good (Fountain, MN)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H05K1/0201G06N10/00H05K1/0225H05K1/09H05K1/18H05K3/02H05K3/32H10N60/81H05K1/023H05K1/115H05K2201/062H05K2201/10363
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Quick Facts
Patent No.
US 12,193,142
App. No.
18/063,136
Granted
Jan 7, 2025
Kind
B2
Abstract

A quantum mechanical circuit includes a substrate; a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor. The third electrical conductor is a poor thermal conductor.

Claims (30)

1. A quantum mechanical circuit comprising:

a substrate;

a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween, wherein the first electrical conductor and the second electrical conductor are electrically decoupled by providing the gap between the first electrical conductor and the second electrical conductor within the substrate; and

a third electrical conductor coupled to the first electrical conductor and the second electrical conductor, wherein the third electrical conductor comprises Copper-Nickel (CuNi) having an electrical resistivity that is approximately 3.8×10−8 Ωm at ambient temperature and a thermal conductivity that is between about 25 W/m° K and 40 W/m° K.

2. The quantum mechanical circuit according to claim 1 , wherein the third electrical conductor further comprises stainless steel.

3. The quantum mechanical circuit according to claim 1 , wherein the first, second and third electrical conductors are configured to transmit a radiofrequency electrical current.

4. The quantum mechanical circuit according to claim 1 , wherein the first electrical conductor and the second electrical conductor comprise copper (Cu).

5. The quantum mechanical circuit of claim 2 , wherein the third electrical conductor is coupled to the substrate using fasteners.

6. The quantum mechanical circuit according to claim 5 , wherein the fasteners comprise brass.

7. The quantum mechanical circuit according to claim 1 , wherein the first electrical conductor and the second electrical conductor are connected to electrical ground.

8. The quantum mechanical circuit according to claim 1 , further comprising attenuator chips electrically coupled to the first electrical conductor and the second electrical conductor.

9. A superconducting quantum mechanical computer comprising:

a refrigeration system comprising a temperature-controlled vessel;

a quantum processor disposed within the temperature-controlled vessel, the quantum processor comprising a plurality of qubits; and

a superconducting circuit disposed inside the temperature-controlled vessel, the superconducting circuit comprising:

a substrate;

a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween, wherein the first electrical conductor and the second electrical conductor are electrically decoupled by providing the gap between the first electrical conductor and the second electrical conductor within the substrate; and

a third electrical conductor coupled to the first electrical conductor and the second electrical conductor, wherein the third electrical conductor comprises Copper-Nickel (CuNi) having an electrical resistivity that is approximately 3.8×10−8 Ωm at ambient temperature and a thermal conductivity that is between about 25 W/m° K and 40 W/m° K.

10. The superconducting quantum mechanical computer according to claim 9 , wherein the third electrical conductor further comprises stainless steel.

11. The superconducting quantum mechanical computer according to claim 9 , wherein the plurality of qubits are provided on the substrate and each of the plurality of qubits is electrically connected to ground via at least one of the first electrical conductor or the second electrical conductor.

12. The superconducting quantum mechanical computer according to claim 9 , wherein the first electrical conductor and the second electrical conductor comprise copper (Cu).

13. The superconducting quantum mechanical computer according to claim 10 , wherein the first, second and third electrical conductor are configured to transmit a radiofrequency electrical current.

14. The superconducting quantum mechanical computer according to claim 10 , wherein the third electrical conductor is coupled to the substrate using fasteners.

15. The superconducting quantum mechanical computer according to claim 9 , wherein the first electrical conductor and the second electrical conductor are connected to electrical ground.

16. The superconducting quantum mechanical computer according to claim 9 , further comprising attenuator chips electrically coupled to the first electrical conductor and the second electrical conductor.

17. The superconducting quantum mechanical computer according to claim 9 , wherein the temperature-controlled vessel is fully enclosed within the refrigeration system.

18. A method of manufacturing a quantum mechanical circuit comprising:

providing a substrate having a top face and a bottom face;

forming a conductive layer on at least one of the top face or the bottom face of the substrate; and

forming conductor lines in a selected pattern on the substrate by removing portions of the conductive layer, the conductor lines including a first electrical conductor and a second electrical conductor on the substrate, the first electrical conductor and the second electrical conductor being spaced apart and separated by a gap therebetween, wherein the first electrical conductor and the second electrical conductor are electrically decoupled by providing the gap between the first electrical conductor and the second electrical conductor within the substrate and by providing blind vias through the substrate that are not aligned with one another to reduce electrical coupling between the first electrical conductor and the second electrical conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2022
From: TIMPANE, TREVOR; BERGE, LAYNE A.; GUMANN, PATRYK; HART, SEAN; LARSEN, CURTIS EUGENE; GOOD, MICHAEL
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 062022/0672 →
Continuity (2)
Continuation 16950610 · Nov 17, 2020
Related Publication 20230199936A1 · Jun 22, 2023
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