IP Library › Granted Patent US 12,167,583

Granted Patent B2

US 12,167,583 · App. 18/064,777 · Granted Dec 10, 2024

Method of forming semiconductor device with increased unit density

Inventors: You-Cheng Xiao (Taichung County, TW); Jhih-Siang Hu (New Taipei, TW); Ru-Yu Wang (New Taipei, TW); Jung-Hsuan Chen (Hsinchu, TW); Ting-Wei Chiang (New Taipei, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

H10B10/18 H01L23/5286 H10B10/12

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Quick Facts

Patent No.: US 12,167,583
App. No.: 18/064,777
Granted: Dec 10, 2024
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

Claims (129)

1. A method, comprising:

abutting a first logic cell having a first cell height to a first memory cell having the first cell height along a first direction;

forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively;

forming a plurality of first conductive rails between the first conductive rail and the second conductive rail along a second direction perpendicular to the first direction;

forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively;

forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail; and

forming a first fin elongated along the first direction in the first logic cell,

wherein an amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails, and

the first fin is partially overlapped with the plurality of second conductive rails in a layout view.

2. The method of claim 1 , further comprising:

abutting a second logic cell having a second cell height to a second memory cell having the second cell height;

abutting the second logic cell and the second memory cell to the first logic cell and the first memory cell, respectively;

forming a fifth conductive rail and the second conductive rail at opposite sides of the second memory cell, respectively;

forming a plurality of third conductive rails between the fifth conductive rail and the second conductive rail;

forming a sixth conductive rail and the fourth conductive rail at opposite sides of the second logic cell, respectively; and

forming a plurality of fourth conductive rails between the sixth conductive rail and the fourth conductive rail,

wherein an amount of the plurality of fourth conductive rails is larger than an amount of the plurality of third conductive rails.

3. The method of claim 1 , further comprising:

forming a second fin and a third fin in the first memory cell;

forming a fourth fin and a fifth fin in the first logic cell;

aligning the second fin and the third fin to the fourth fin and the fifth fin, respectively;

coupling a fifth conductive rail of the plurality of first conductive rails to each of the second fin and the third fin;

disposing a sixth conductive rail of the plurality of second conductive rails over the fourth fin; and

disposing a seventh conductive rail of the plurality of second conductive rails over the fifth fin,

wherein the sixth conductive rail is adjacent to the seventh conductive rail, and

the fourth fin is adjacent to the fifth fin.

4. The method of claim 3 , further comprising:

forming a sixth fin in the first memory cell; and

forming a seventh fin and an eighth fin in the first logic cell,

wherein the seventh fin and the eighth fin are adjacent with each other and extend along the first direction, and

the sixth fin is disposed between the seventh fin and the eighth fin along the second direction.

5. The method of claim 4 , further comprising:

disposing an eighth conductive rail of the plurality of first conductive rails over the sixth fin;

disposing a ninth conductive rail of the plurality of second conductive rails over the seventh fin; and

disposing a tenth conductive rail of the plurality of second conductive rails over the seventh fin,

wherein the ninth conductive rail and the tenth conductive rail are adjacent with each other, and

the eighth conductive rail is between the fifth conductive rail and the first conductive rail.

6. The method of claim 5 , further comprising:

disposing a eleventh conductive rail of between the tenth conductive rail and the sixth conductive rail; and

separating the eleventh conductive rail from each of the eighth fin and the fourth fin.

7. The method of claim 1 , further comprising:

forming a second fin in the first logic cell; and

forming a third fin in the first memory cell,

wherein the first fin and the second fin are adjacent with each other and extend along the first direction, and

the third fin is disposed between the first fin and the second fin along the second direction.

8. The method of claim 7 , further comprising:

disposing a fifth conductive rail of the plurality of first conductive rails over the third fin;

disposing a sixth conductive rail of the plurality of second conductive rails over the second fin; and

disposing a seventh conductive rail of the plurality of second conductive rails over the third fin,

wherein the sixth conductive rail and the seventh conductive rail are adjacent with each other.

9. A method, comprising:

abutting a first logic cell having a first cell height to a first memory cell having the first cell height;

forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively;

forming a plurality of first conductive rails between the first conductive rail and the second conductive rail;

forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively;

forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail;

forming a second logic cell abutted to a second memory cell and abutted to the first logic cell;

forming a fifth conductive rail and the second conductive rail at opposite sides of the second memory cell, respectively;

forming a plurality of third conductive rails between the fifth conductive rail and the second conductive rail;

forming a sixth conductive rail and the fourth conductive rail at opposite sides of the second logic cell, respectively; and

forming a plurality of fourth conductive rails between the sixth conductive rail and the fourth conductive rail,

wherein an amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails,

an amount of the plurality of fourth conductive rails is larger than an amount of the plurality of third conductive rails,

the second memory cell is different from the first memory cell, and

the fifth conductive rail is different from the first conductive rail.

10. The method of claim 9 , further comprising:

forming a first fin and a second fin in the first memory cell;

forming a third fin and a fourth fin in the first logic cell;

forming a seventh conductive rail of the plurality of first conductive rails coupled to each of the first fin and the second fin;

forming an eighth conductive rail of the plurality of second conductive rails disposed over the third fin; and

forming a ninth conductive rail of the plurality of second conductive rails disposed over the fourth fin,

wherein the eighth conductive rail is adjacent to the ninth conductive rail,

the first fin and the second fin are aligned to the third fin and the fourth fin, respectively, and

the third fin is adjacent to the fourth fin.

11. The method of claim 10 , further comprising:

forming a fifth fin in the first memory cell; and

forming a sixth fin and a seventh fin in the first logic cell,

wherein the sixth fin and the seventh fin are adjacent with each other and extend along a first direction, and

the fifth fin is disposed between the sixth fin and the seventh fin along a second direction different from the first direction.

12. The method of claim 11 , further comprising:

forming a tenth conductive rail of the plurality of first conductive rails disposed over the fifth fin;

forming an eleventh conductive rail of the plurality of second conductive rails disposed over the sixth fin; and

forming a twelfth conductive rail of the plurality of second conductive rails disposed over the sixth fin,

wherein the eleventh conductive rail and the twelfth conductive rail are adjacent with each other, and

the tenth conductive rail is between the seventh conductive rail and the first conductive rail.

13. The method of claim 12 , further comprising:

forming a thirteenth conductive rail of the plurality of second conductive rails disposed between the twelfth conductive rail and the eighth conductive rail,

wherein the thirteenth conductive rail is separated from each of the seventh fin and the third fin.

14. The method of claim 9 , further comprising:

forming a first fin and a second fin in the first logic cell; and

forming a third fin in the first memory cell,

wherein the first fin and the second fin are adjacent with each other and extend along a first direction, and

the third fin is disposed between the first fin and the second fin along a second direction different from the first direction.

15. The method of claim 14 , further comprising:

forming a seventh conductive rail of the plurality of first conductive rails disposed over the third fin;

forming a eighth conductive rail of the plurality of second conductive rails disposed over the second fin; and

forming a ninth conductive rail of the plurality of second conductive rails disposed over the third fin,

wherein the eighth conductive rail and the ninth conductive rail are adjacent with each other.

16. A method, comprising:

abutting a first logic cell having a first cell height to a first memory cell having the first cell height;

forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively;

forming a plurality of first conductive rails between the first conductive rail and the second conductive rail;

forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively;

forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail;

forming a first fin and a second fin in the first memory cell; and

forming a third fin and a fourth fin in the first logic cell;

wherein an amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails,

the first fin and the second fin are aligned to the third fin and the fourth fin, respectively,

the third fin is adjacent to the fourth fin,

the first fin and the second fin are disposed between the first conductive rail and the second conductive rail, and

the third fin and the fourth fin are disposed between the third conductive rail and the fourth conductive rail.

17. The method of claim 16 , further comprising:

forming a fifth conductive rail of the plurality of first conductive rails coupled to each of the first fin and the second fin.

18. The method of claim 17 , further comprising:

forming a fifth fin in the first memory cell; and

forming a sixth fin and a seventh fin in the first logic cell,

wherein the sixth fin and the seventh fin are adjacent with each other and extend along a first direction, and

the fifth fin is disposed between the sixth fin and the seventh fin along a second direction different from the first direction.

19. The method of claim 18 , further comprising:

forming a sixth conductive rail of the plurality of first conductive rails disposed over the fifth fin;

forming a seventh conductive rail of the plurality of second conductive rails disposed over the sixth fin; and

forming a eighth conductive rail of the plurality of second conductive rails disposed over the sixth fin,

wherein the seventh conductive rail and the eighth conductive rail are adjacent with each other, and

the sixth conductive rail is between the fifth conductive rail and the first conductive rail.

20. The method of claim 16 , further comprising:

forming a fifth fin and a sixth fin in the first logic cell; and

forming a seventh fin in the first memory cell,

wherein the fifth fin and the sixth fin are adjacent with each other and extend along a first direction, and

the seventh fin is disposed between the fifth fin and the sixth fin along a second direction different from the first direction.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2022

From: XIAO, YOU-CHENG; HU, JHIH-SIANG; WANG, RU-YU; CHEN, JUNG-HSUAN; CHIANG, TING-WEI

To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Reel/Frame 062143/0881 →

Continuity (2)

Continuation 17035438 · Sep 28, 2020

Related Publication 20230111939A1 · Apr 13, 2023