Image sensor including stacked chips
An image sensor includes a first lower chip, and an upper chip on and bonded to the first lower chip. The first lower chip and the upper chip collectively provide a plurality of pixels. A respective pixel of the plurality of pixels includes a photoelectric conversion element, a floating diffusion region, a ground region, and a transfer gate in the upper chip, and a plurality of lower transistors in the first lower chip. A first lower transistor among the plurality of lower transistors includes a plurality of first channel layers stacked vertically, and a first gate on the plurality of first channel layers.
1 . An image sensor comprising:
a first lower chip; and
an upper chip on and bonded to the first lower chip,
wherein the first lower chip and the upper chip collectively comprise a plurality of pixels,
wherein a respective pixel of the plurality of pixels comprises:
a photoelectric conversion element, a floating diffusion region, a ground region, and a transfer gate in the upper chip; and
a plurality of lower transistors in the first lower chip, and
wherein a first lower transistor among the plurality of lower transistors comprises a plurality of first channel layers stacked vertically, and a first gate on the plurality of first channel layers,
wherein the upper chip further comprises:
a semiconductor substrate having a first surface and a second surface opposing each other;
an insulating structure on the second surface of the semiconductor substrate;
pixel isolation structures in the semiconductor substrate; and
color filters on the insulating structure,
wherein the photoelectric conversion element is in the semiconductor substrate, between the pixel isolation structures, and
the floating diffusion region and the ground region are in the semiconductor substrate adjacent to the first surface.
2 . The image sensor of claim 1 , wherein the first lower transistor comprises a source/drain electrically connected to the floating diffusion region and vertically overlapping the floating diffusion region.
3 . The image sensor of claim 1 , wherein a second lower transistor among the plurality of lower transistors has a channel structure comprising first semiconductor layers and second semiconductor layers that are alternately stacked, and a second gate on side surfaces and an upper surface of the channel structure, and
wherein a first material of the first semiconductor layers and a second material of the second semiconductor layers are different from each other.
4 . The image sensor of claim 1 , wherein the upper chip comprises an upper interconnection structure and upper bonding pads electrically connected to the upper interconnection structure, and the first lower chip comprises a lower interconnection structure and lower bonding pads electrically connected to the lower interconnection structure,
wherein the lower bonding pads are bonded to the upper bonding pads, and
among the lower bonding pads and the upper bonding pads, any one lower bonding pad and any one upper bonding pad bonded to each other vertically overlap the floating diffusion region.
5 . The image sensor of claim 4 , wherein the upper chip further comprises:
a ground contact electrically connected to the ground region;
a floating diffusion contact electrically connected to the floating diffusion region; and
a transfer gate contact electrically connected to a transfer gate electrode of the transfer gate,
wherein the ground contact, the floating diffusion contact, and the transfer gate contact are electrically connected to the upper bonding pads by the upper interconnection structure.
6 . The image sensor of claim 1 , wherein the upper chip further comprises a device isolation layer between the ground region and the floating diffusion region, and
at least a portion of the transfer gate is in a region recessed in a direction from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate.
7 . The image sensor of claim 1 , wherein the floating diffusion region comprises a pillar portion, and
the transfer gate is on at least a portion of a side surface of the pillar portion of the floating diffusion region.
8 . The image sensor of claim 1 , further comprising an upper transistor in the upper chip,
wherein the upper transistor comprises a plurality of upper channel layers vertically stacked, and an upper gate structure on the plurality of upper channel layers.
9 . The image sensor of claim 8 , wherein the floating diffusion region comprises first semiconductor layers and second semiconductor layers that are alternately stacked,
wherein a first material of the first semiconductor layers and a second material of the second semiconductor layers are different from each other.
10 . The image sensor of claim 1 , wherein the first lower transistor comprises a reset transistor, a selection transistor, or a driving transistor of the respective pixel, and the image sensor further comprising:
a second lower chip below the first lower chip,
wherein the second lower chip comprises a circuit configured to control a pixel array comprising the plurality of pixels.
11 . The image sensor of claim 10 , wherein the upper chip is free of the reset transistor, the selection transistor, and/or the driving transistor of the respective pixel,
wherein the circuit of the second lower chip comprises transistors having at least one of a first three-dimensional (3D) transistor structure or a second three-dimensional (3D) transistor structure,
wherein the first 3D transistor structure comprises a plurality of lower channel layers vertically stacked, and a first lower gate on the plurality of lower channel layers, and
wherein the second 3D transistor structure has a lower channel structure comprising first lower semiconductor layers and second lower semiconductor layers that are alternately stacked, and a second lower gate on side surfaces and an upper surface of the lower channel structure.
12 . An image sensor comprising:
a first lower chip;
an upper chip on and bonded to the first lower chip; and
a second lower chip bonded to the first lower chip, below the first lower chip,
wherein the first lower chip and the upper chip collectively comprise a pixel array having a plurality of pixels,
wherein the second lower chip comprises a control circuit configured to control the pixel array,
wherein a respective pixel of the plurality of pixels comprises a photoelectric conversion element, a floating diffusion region, a ground region, a transfer gate, a reset transistor, a selection transistor, and a driving transistor,
wherein the upper chip comprises the photoelectric conversion element, the floating diffusion region, the ground region, and the transfer gate,
wherein the first lower chip comprises at least one transistor among the reset transistor, the selection transistor, or the driving transistor,
wherein the at least one transistor of the first lower chip has a first three-dimensional transistor structure comprising a plurality of first channel layers stacked vertically, and a first gate on the plurality of first channel layers,
wherein the upper chip comprises an upper bonding pad and the first lower chip comprises a lower bonding pad bonded to the upper bonding pad,
wherein the at least one transistor comprises a source/drain electrically connected to the floating diffusion region, and
wherein at least one of the upper bonding pad, the lower bonding pad, or the source/drain vertically overlaps the floating diffusion region.
13 . The image sensor of claim 12 , wherein the at least one transistor is the driving transistor.
14 . The image sensor of claim 12 , wherein in the first lower chip, the reset transistor, the selection transistor, and the driving transistor comprise the first three-dimensional transistor structure and a second three-dimensional transistor structure different from the first three-dimensional transistor structure,
wherein the second three-dimensional transistor structure has a channel structure comprising first semiconductor layers and second semiconductor layers that are alternately stacked, and a second gate on side surfaces and an upper surface of the channel structure, and
a first material of the first semiconductor layers and a second material of the second semiconductor layers are different from each other.
15 . The image sensor of claim 14 , wherein the upper chip is free of the reset transistor, the selection transistor, and/or the driving transistor of the respective pixel, and wherein the control circuit of the second lower chip comprises transistors of the first three-dimensional transistor structure and the second three-dimensional transistor structure.
16 . An image sensor comprising:
a first lower chip;
an upper chip on and bonded to the first lower chip; and
a second lower chip bonded to the first lower chip, below the first lower chip,
wherein the first lower chip and the upper chip collectively comprise a pixel array having a plurality of pixels,
wherein the second lower chip comprises a control circuit configured to control the pixel array,
wherein a respective pixel of the plurality of pixels comprises a photoelectric conversion element, a floating diffusion region, a ground region, a transfer gate, a reset transistor, a selection transistor, and a driving transistor,
wherein the upper chip comprises the photoelectric conversion element, the floating diffusion region, the ground region, and the transfer gate,
wherein the first lower chip comprises at least a first transistor among the reset transistor, the selection transistor, or the driving transistor,
wherein the upper chip further comprises:
an upper semiconductor substrate having a first surface and a second surface opposing each other;
color filters on the second surface of the upper semiconductor substrate;
pixel isolation structures in the upper semiconductor substrate;
an upper insulating structure below the first surface of the upper semiconductor substrate; and
upper bonding pads in the upper insulating structure and having lower surfaces coplanar with a lower surface of the upper insulating structure,
wherein the photoelectric conversion element is in the upper semiconductor substrate, between the pixel isolation structures,
wherein the floating diffusion region and the ground region are in the upper semiconductor substrate adjacent to the first surface of the upper semiconductor substrate,
wherein the first lower chip further comprises:
a first lower semiconductor substrate;
a first lower insulating structure on the first lower semiconductor substrate;
first lower bonding pads in the first lower insulating structure and having upper surfaces coplanar with an upper surface of the first lower insulating structure; and
a lower protective insulating layer below the first lower semiconductor substrate,
wherein the second lower chip further comprises:
a second lower semiconductor substrate; and
a second lower insulating structure on the second lower semiconductor substrate,
wherein the first lower bonding pads and the upper bonding pads are in contact with each other, and
wherein the first transistor of the first lower chip has a first three-dimensional transistor structure comprising a plurality of first channel layers vertically stacked, and a first gate on the plurality of first channel layers,
wherein a second transistor of the first lower chip has a channel structure comprising first semiconductor layers and second semiconductor layers that are alternately stacked, and a second gate on side surfaces and an upper surface of the channel structure, and
wherein a first material of the first semiconductor layers and a second material of the second semiconductor layers are different from each other.
17 . The image sensor of claim 16 , wherein in the first lower chip, the reset transistor, the selection transistor, and the driving transistor comprise the first three-dimensional transistor structure and a second three-dimensional transistor structure of the second transistor,
wherein the second three-dimensional transistor structure is different from the first three-dimensional transistor structure, and
wherein the second three-dimensional transistor structure has the channel structure comprising the first semiconductor layers and the second semiconductor layers that are alternately stacked, and the second gate on the side surfaces and the upper surface of the channel structure.
18 . The image sensor of claim 16 , wherein the upper chip further comprises:
an upper interconnection structure in the upper insulating structure;
an upper through-electrode structure penetrating the upper semiconductor substrate and in contact with the upper interconnection structure; and
a pad pattern on the upper through-electrode structure,
wherein the first lower chip further comprises:
a first lower interconnection structure in the first lower insulating structure; and
a lower through-electrode structure penetrating the first lower semiconductor substrate,
wherein the pixel isolation structures comprise a first line portion extending in a first direction, a second line portion extending in a second direction intersecting the first direction, and an intersection region on which the first line portion and the second line portion intersect, and
wherein the lower through-electrode structure vertically overlaps the intersection region.
19 . The image sensor of claim 16 , further comprising:
an upper through-electrode structure penetrating a pad area of the upper chip and extending into the first lower chip,
wherein the first lower chip further comprises:
a first lower interconnection structure in the first lower insulating structure; and
a lower through-electrode structure penetrating the first lower semiconductor substrate,
wherein the pixel isolation structures comprise a first line portion extending in a first direction, a second line portion extending in a second direction intersecting the first direction, and an intersection region on which the first line portion and the second line portion intersect,
wherein the lower through-electrode structure vertically overlaps the intersection region, and
wherein the upper through-electrode structure is electrically connected to the first lower interconnection structure.
20 . The image sensor of claim 16 , wherein at least one of the first transistor of the first lower chip or the second transistor of the first lower chip comprises a source/drain electrically connected to the floating diffusion region and vertically overlapping the floating diffusion region.