Solid-state imaging device configured by electrically bonding the respective electrodes of a plurality of semiconductor chips
An imaging device includes a first chip ( 72 ). The first chip includes first and second pixels including respective first and second photoelectric conversion regions (PD) that convert incident light into electric charge. The first chip includes a first connection region for bonding the first chip to a second chip ( 73 ) and including a first connection portion ( 702, 702 d ) overlapped with the first photoelectric conversion region in a plan view, and a second connection portion overlapped with the second photoelectric conversion region in the plan view. The first photoelectric region receives incident light of a first wavelength, and the second photoelectric conversion region receives incident light of a second wavelength that is greater than the first wavelength. The first connection portion overlaps an area of the first photoelectric conversion region that is larger than an area of the second photoelectric conversion region overlapped by the second connection portion.
1. An imaging device, comprising:
a first chip, including:
first, second, third, and fourth pixels including respective first, second, third, and fourth photoelectric conversion regions that convert incident light into electric charge, wherein the first, second, third, and fourth pixels output pixel signals based on the electric charge; and
a first connection region for bonding the first chip to a second chip and including a first connection portion overlapped with the first photoelectric conversion region in a plan view, and a second connection portion overlapped with the second photoelectric conversion region in the plan view,
wherein the first photoelectric conversion region receives incident light of a first wavelength, and the second photoelectric conversion region receives incident light of a second wavelength that is greater than the first wavelength,
wherein, in the plan view, an area of the first connection portion is larger than an area of the second connection portion, and
wherein, in the plan view, the first connection region does not overlap the third photoelectric conversion region or the fourth photoelectric conversion region.
2. The imaging device of claim 1 , further comprising:
a logic circuit, included in the second chip, to process the pixel signals from the first, second, third, and fourth pixels; and
a second connection region including a third connection portion overlapped with the first photoelectric conversion region in the plan view, and a fourth connection portion overlapped with the second photoelectric conversion region in the plan view,
wherein the first connection portion is bonded to the third connection portion, and the second connection portion is bonded to the fourth connection portion.
3. The imaging device of claim 2 , wherein the first, second, third, and fourth connection portions are bonding pads.
4. The imaging device of claim 3 , wherein the bonding pads include copper.
5. The imaging device of claim 3 , wherein one of the first connection portion and the second connection portion is a dummy bonding pad.
6. The imaging device of claim 2 , wherein the first, second, third, and fourth connection portions each include a plurality of connection portions.
7. The imaging device of claim 1 , wherein the first photoelectric conversion region and the second photoelectric conversion region share a floating diffusion.
8. The imaging device of claim 7 , wherein the first chip includes:
a wiring between the first connection portion and the first photoelectric conversion region, and wherein the wiring is coupled to a node that receives a voltage to adjust a parasitic capacitance of the floating diffusion.
9. The imaging device of claim 1 , wherein the first wavelength corresponds to blue light, and the second wavelength corresponds to red or green light.
10. The imaging device of claim 1 , wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are part of a plurality of pixels arranged in a matrix at a central region of the first chip, and wherein the first connection portion and the second connection portion are part of a plurality of connection portions arranged in the matrix at the central region of the first chip.