Image sensor pixel structure employing a shared floating diffusion
A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.
1. An image sensor pixel structure comprising:
a semiconductor substrate including a shallow trench isolation structure and a semiconductor material portion, wherein said shallow trench isolation structure laterally encloses said semiconductor material portion, said semiconductor material portion has a contiguous semiconductor surface and includes four photodiodes, four channel regions, and a common floating diffusion region, said contiguous semiconductor surface extends over an entirety of said semiconductor material portion, each of said four channel regions is directly adjoined to one of said four photodiodes and to said common floating diffusion region; and
four gate stacks overlying each of said four channel regions, wherein each of said four gate stacks includes a gate dielectric and a gate electrode, and wherein said four photodiodes, said four channel regions, said common floating diffusion region, and said four gate stacks constitute four field effect transistors in which said common floating diffusion region constitutes a common drain.
2. The image sensor pixel structure of claim 1 , wherein said four photodiodes are located within four different quadrants as defined employing a first vertical line passing through a first point within said common floating diffusion region as a center axis, and said first vertical line is perpendicular to said contiguous semiconductor surface.
3. The image sensor pixel structure of claim 2 , further comprising a reset gate transistor, a source follower transistor, and a row select transistor that are located on said semiconductor substrate, wherein said common floating diffusion region, said reset gate transistor, said source follower transistor, and said row select transistor are located within four different quadrants as defined employing a second vertical line passing through a second point within one of said four photodiodes as a center axis, and said second vertical line is perpendicular to said contiguous semiconductor surface.
4. The image sensor pixel structure of claim 3 , further comprising a contiguous metal wiring structure and contact vias that resistively connect a drain region of said reset gate transistor and a drain region of another source follower transistor.
5. The image sensor pixel structure of claim 3 , further comprising a first contiguous metal wiring structure that overlies a portion of said common floating diffusion region, a source region of said reset gate transistor, and a gate electrode of said source follower transistor, wherein said first contiguous metal wiring structure provides a path for a resistive electrical connection between said common floating diffusion region and a source region of said reset gate transistor.
6. The image sensor pixel structure of claim 5 , further comprising first contact vias, wherein each of said first contact vias vertically contacts said first contiguous metal wiring structure and one of said common floating diffusion region, said source region of said reset gate transistor, and said gate electrode of said source follower transistor.
7. The image sensor pixel structure of claim 5 , further comprising a second contiguous metal wiring structure that overlies a source region of said source follower transistor and a drain region of said row select transistor.
8. The image sensor pixel structure of claim 7 , further comprising second contact vias, wherein each of said second contact vias vertically contacts said second contiguous metal wiring structure and one of said source region of said source follower transistor and said drain region of said row select transistor.
9. The image sensor pixel structure of claim 7 , further comprising another contiguous metal wiring structure and additional contact vias that resistively connect a drain region of said reset gate transistor and a drain region of another source follower transistor.
10. The image sensor pixel structure of claim 3 , wherein a quadrant as defined employing said second vertical line and including said common floating diffusion region is located immediately adjacent to a quadrant as defined employing said second vertical line and including said reset gate transistor and is located immediately adjacent to another quadrant as defined employing said second vertical line and including said row select transistor.
11. The image sensor pixel structure of claim 3 , further comprising:
a first optically-transparent dielectric layer embedding at least one contiguous metal wiring structure that provides resistive electrical connections among said common floating diffusion region, said reset gate transistor, said source follower transistor, and said row select transistor, wherein said at least one contiguous metal wiring structure does not overlie any of said four photodiodes; and
at least another optically-transparent dielectric layer overlying said first dielectric layer.
12. The image sensor pixel structure of claim 1 , wherein each of said four gate electrodes is not resistively connected to any other of said four gate electrodes.
13. The image sensor pixel structure of claim 1 , wherein an entirety of said semiconductor material portion is a single crystalline silicon-containing material.
14. A method of operating a semiconductor circuit embodied in a semiconductor structure, said method comprising:
providing a semiconductor structure including an image sensor pixel structure of claim 1 ;
generating electrical charges in a first photodiode among said four photodiodes; and
transferring electrical charges from said first photodiode to said common floating diffusion region, while a second photodiode, a third photodiode, and a fourth photodiode among said four photodiodes are electrically isolated from said common floating diffusion region.
15. The method of claim 14 , further comprising:
generating electrical charges in each of said second photodiode, said third photodiode, and said fourth photodiode; and
sequentially transferring electrical charges from each of said second photodiode, said third photodiode, and said fourth photodiode to said common floating diffusion region, wherein three of said four photodiodes are electrically isolated during each charge transfer into said common floating diffusion region.
16. The method of claim 15 , wherein said image sensor pixel structure further comprises a reset gate transistor, a source follower transistor, and a row select transistor that are located on said semiconductor substrate, wherein said common floating diffusion region, said reset gate transistor, said source follower transistor, and said row select transistor are located within four different quadrants as defined employing a second vertical line passing through a second point within one of said four photodiodes as a center axis, and said second vertical line is perpendicular to said contiguous semiconductor surface, and wherein said method further comprises:
turning on and turning off said reset gate transistor prior to each transferring of electrical charges into said common floating diffusion region; and
determining a voltage level at a source region of said row select transistor after each transferring of electrical charges into said common floating diffusion region.