Method to reduce breakdown failure in a MIM capacitor
Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.
1. A metal-insulator-metal (MIM) capacitor comprising:
a bottom electrode comprising a metal element and a non-metal element, wherein the non-metal element is different than oxygen;
a dielectric layer overlying the bottom electrode;
a top electrode overlying the dielectric layer; and
an interfacial layer between, and directly contacting, the bottom electrode and the dielectric layer, wherein the interfacial layer comprises oxide of the bottom electrode, the metal element, and the non-metal element;
wherein an atomic percentage of oxygen in the interfacial layer decreases in a direction along a thickness of the interfacial layer, whereas an atomic percentage of the non-metal element in the interfacial layer increases in the direction along the thickness.
2. The MIM capacitor according to claim 1 , wherein the atomic percentage of oxygen decreases from a top surface of the interfacial layer to a bottom surface of the interfacial layer, and wherein the atomic percentage of the non-metal element increases from the top surface of the interfacial layer to the bottom surface of the interfacial layer.
3. The MIM capacitor according to claim 1 , wherein the bottom electrode, the interfacial layer, and the dielectric layer share a common width.
4. The MIM capacitor according to claim 1 , wherein the interfacial layer is conductive.
5. The MIM capacitor according to claim 1 , wherein the bottom electrode, the interfacial layer, and the dielectric layer have individual sidewalls arranged edge to edge to form a common sidewall.
6. The MIM capacitor according to claim 1 , wherein the interfacial layer is titanium oxynitride, the metal element is titanium, and the non-metal element is nitrogen.
7. The MIM capacitor according to claim 1 , wherein adhesion strength between the interfacial layer and the bottom electrode is greater than about 1000 micronewtons to prevent delamination.
8. A metal-insulator-metal (MIM) capacitor comprising:
a bottom electrode comprising a metal element and a non-metal element, wherein the non-metal element is different than oxygen;
a dielectric layer overlying the bottom electrode;
a top electrode overlying the dielectric layer; and
an interfacial layer between, and directly contacting, the bottom electrode and the dielectric layer, wherein the interfacial layer comprises oxide of the bottom electrode, the metal element, and the non-metal element;
wherein the interfacial layer has a pair of first sidewalls respectively on opposite sides of the MIM capacitor and extending from a top surface of the interfacial layer, and wherein the bottom electrode has a pair of second sidewalls respectively on the opposite sides and separated by substantially a same distance as the first sidewalls.
9. The MIM capacitor according to claim 8 , wherein the dielectric layer is between and directly contacts the top electrode and the interfacial layer.
10. The MIM capacitor according to claim 8 , wherein an atomic percentage of oxygen in the interfacial layer is greater at the top surface of the interfacial layer than at a bottom surface of the interfacial layer.
11. The MIM capacitor according to claim 8 , wherein an atomic percentage of the non-metal element in the interfacial layer is greater at a bottom surface of the interfacial layer than at the top surface of the interfacial layer.
12. The MIM capacitor according to claim 8 , wherein a thickness of the interfacial layer is about 20-50 angstroms.
13. The MIM capacitor according to claim 8 , wherein the second sidewalls are respectively edge to edge with the first sidewalls.
14. The MIM capacitor according to claim 8 , wherein the bottom electrode, the interfacial layer, and the dielectric layer have individual U-shaped profiles, and wherein top surfaces respectively of the U-shaped profiles are level with each other and a top surface of the top electrode.
15. An integrated circuit (IC) chip comprising a metal-insulator-metal (MIM) capacitor, wherein the MIM capacitor comprises:
a bottom electrode comprising a metal nitride;
a metal oxide layer overlying the bottom electrode;
a top electrode overlying and directly contacting the metal oxide layer; and
a metal oxynitride layer between, and directly contacting, the bottom electrode and the metal oxide layer, wherein the metal oxynitride layer comprises the metal nitride and has a higher atomic percentage of oxygen than nitrogen at a bottom surface of the metal oxynitride layer.
16. The IC chip according to claim 15 , wherein the metal oxynitride layer has the higher atomic percentage of oxygen than nitrogen at a top surface of the metal oxynitride layer.
17. The IC chip according to claim 15 , wherein the metal oxynitride layer is TiO x N y , wherein x and y are numbers, wherein x>y, and wherein x is less than 2 and greater than 0.
18. The IC chip according to claim 15 , wherein a top surface of the bottom electrode and the top surface of the metal oxynitride layer share a common width.
19. The IC chip according to claim 15 , further comprising:
a first wire and a second wire underlying the MIM capacitor at a first common elevation;
a third wire and a fourth wire overlying the MIM capacitor at a second common elevation;
a first via and a second via extending from the MIM capacitor respectively to the first and third wires; and
a third via extending from the second wire to the fourth wire.
20. The IC chip according to claim 19 , further comprising:
a semiconductor substrate; and
a transistor on the semiconductor substrate, wherein the first wire and the second wire are spaced over the transistor, and wherein the first wire is electrically coupled to the transistor.