Multi-layer chip architecture and fabrication
A method includes providing a first chip having a circuit element layer stack, the circuit element layer stack including a plurality of circuit elements distributed across a plurality of layers. The circuit element layer stack has a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers and a coherent device layer disposed on the circuit element layer stack. The method includes removing the sacrificial material.
1 . A method for fabricating a qubit control chip, the method comprising:
providing a first substrate having a first layer on a surface of the first substrate, wherein the first layer has a dielectric loss tangent for microwave frequencies of less than 10 −5 ;
forming a plurality of layers into a circuit element layer stack on a first surface of the first layer,
wherein the circuit element layer stack comprises a plurality of circuit element layers, wherein the plurality of circuit element layers comprises a plurality of circuit elements, wherein the plurality of circuit elements comprise a superconductor material;
after forming the plurality of layers into the circuit element layer stack on the first layer, bonding a second substrate to a surface of the circuit element layer stack, wherein the surface of the circuit element layer stack is on an opposite side of the circuit element layer stack from the first layer;
after bonding the second substrate to the surface of the circuit element layer stack, removing the first substrate to expose a second surface of the first layer, the second surface being on an opposite side of the first layer from the first surface; and
forming a qubit control element or a qubit readout element on the second surface of the first layer.
2 . The method of claim 1 , wherein the second substrate, the circuit element layer stack, the first layer, and the qubit control element or the qubit readout element are included in a first chip, and wherein the method comprises:
bonding a second chip to the first chip with the qubit control element or the qubit readout element facing the second chip, wherein the qubit control element or the qubit readout element is separated from the second chip by a gap.
3 . The method of claim 2 ,
wherein the second chip comprises a qubit arranged to couple to the qubit control element or the qubit readout element.
4 . The method of claim 1 , comprising:
forming a via through the first layer, the via electrically coupling the qubit control element or the qubit readout element to a first circuit element of the plurality of circuit elements.
5 . The method of claim 4 , wherein forming the via through the first layer comprises:
subsequent to removing the first substrate, forming an aperture in the first layer; and
forming the via in the aperture.
6 . The method of claim 4 , wherein forming the via through the first layer comprises, prior to bonding the second substrate to the surface of the circuit element layer stack:
forming an aperture in the first layer from the first surface of the first layer; and
forming the via in the aperture.
7 . The method of claim 1 , wherein bonding the second substrate to the surface of the circuit element layer stack comprises:
forming a first metal layer on a surface of the second substrate;
forming a second metal layer on the surface of the circuit element layer stack; and
bonding the first metal layer to the second metal layer.
8 . The method of claim 1 , wherein the first substrate comprises a dielectric layer between the surface of the first substrate and the first layer, and
wherein removing the first substrate further comprises removing the dielectric layer.
9 . The method of claim 1 , wherein removing the first substrate comprises etching the first substrate.
10 . The method of claim 1 , comprising:
transferring a structure comprising the circuit element layer stack, the first layer, and the second substrate from a first fabrication tool to a second fabrication tool or within a fabrication tool,
wherein transferring the structure comprises contacting the second substrate.
11 . The method of claim 1 , wherein the circuit element layer stack comprises a filler material filling a space between the plurality of circuit elements.
12 . The method of claim 1 , wherein the circuit element layer stack comprises a thermalization structure composed of one or more non-superconductor metals.
13 . The method of claim 1 , wherein the first layer is a monocrystalline silicon layer.
14 . The method of claim 2 , wherein the first layer is a monocrystalline semiconductor layer, and
wherein the first substrate comprises an intermediate layer in contact with the second surface of the first layer, wherein the intermediate layer comprises a dielectric material.
15 . The method of claim 1 , wherein forming the plurality of layers into the circuit element layer stack on the first surface of the first layer comprises performing, on the plurality of layers while the plurality of layers are on the first surface of the first layer:
at least one of physical layer deposition or chemical deposition;
at least one of photolithography or electron-beam lithography; and
at least one of wet-chemical etching or plasma etching.