Diffusion break structure for transistors
A semiconductor device includes a first gate region and a second gate region. A diffusion break region is between the first gate region and the second gate region. A top surface of the diffusion break region is co-planar with at least one of a top surface of one or more gate contacts and a top surface of one or more source/drain contacts.
1 . A semiconductor device, comprising:
a first gate region;
a second gate region;
a first gate contact on the first gate region;
a second gate contact on the second gate region; and
a diffusion break region between the first gate region and the second gate region, a first edge of the diffusion break region abutting an edge of the first gate contact and a second edge of the diffusion break region abutting an edge of the second gate contact;
wherein a top surface of the diffusion break region is co-planar with at least one of a top surface of one or more gate contacts and a top surface of one or more source/drain contacts.
2 . The semiconductor device of claim 1 ,
wherein the top surface of the diffusion break region is co-planar with a top surface of the first gate contact and a top surface of the second gate contact.
3 . The semiconductor device of claim 1 , wherein the diffusion break region is disposed between the first gate contact and the second gate contact.
4 . The semiconductor device of claim 1 , wherein the first gate contact and second gate contact are cross-coupled with a first source/drain contact and a second source/drain contact, respectively.
5 . The semiconductor device of claim 1 , further comprising:
a first source/drain region;
a second source/drain region;
a first source/drain contact on the first source/drain region; and
a second source/drain contact on the second source/drain region;
wherein the top surface of the diffusion break region is co-planar with a top surface of the first source/drain contact and a top surface of the second source/drain contact.
6 . The semiconductor device of claim 5 , wherein the diffusion break region is disposed between the first source/drain contact and the second source/drain contact.
7 . The semiconductor device of claim 6 , wherein a first edge of the diffusion break region abuts an edge of the first source/drain contact and a second edge of the diffusion break region abuts an edge of the second source/drain contact.
8 . The semiconductor device of claim 6 , wherein the first source/drain contact corresponds to a supply voltage and the second source/drain contact corresponds to a bitline voltage.
9 . The semiconductor device of claim 1 , wherein a bottom surface of the diffusion break region is under at least one of a bottom surface of the one or more gate contacts and a bottom surface of the one or more source/drain contacts.
10 . The semiconductor device of claim 1 , wherein the diffusion break region comprises a double diffusion break region.
11 . The semiconductor device of claim 1 , wherein the one or more gate contacts and the one or more source/drain contacts comprise middle-of-line contacts.
12 . A semiconductor device, comprising:
a first gate region;
a second gate region;
a first gate contact on the first gate region;
a second gate contact on the second gate region; and
a double diffusion break region between the first gate region and the second gate region, a first edge of the double diffusion break region abutting an edge of the first gate contact and a second edge of the double diffusion break region abutting an edge of the second gate contact;
wherein a top surface of the double diffusion break region is above a top surface of the first gate region and above a top surface of the second gate region.
13 . The semiconductor device of claim 12 ,
wherein the top surface of the double diffusion break region is co-planar with a top surface of the first gate contact and a top surface of the second gate contact.
14 . The semiconductor device of claim 12 , wherein the double diffusion break region is disposed between the first gate contact and the second gate contact.
15 . The semiconductor device of claim 12 , wherein the first gate contact and second gate contact are cross-coupled with a first source/drain contact and a second source/drain contact, respectively.
16 . The semiconductor device of claim 12 , further comprising:
a first source/drain region;
a second source/drain region;
a first source/drain contact on the first source/drain region; and
a second source/drain contact on the second source/drain region;
wherein the top surface of the double diffusion break region is co-planar with a top surface of the first source/drain contact and a top surface of the second source/drain contact.
17 . The semiconductor device of claim 12 , wherein a bottom surface of the double diffusion break region is under at least one of a bottom surface of one or more of the first and second gate contacts and a bottom surface of one or more source/drain contacts.
18 . A semiconductor device, comprising:
a first gate contact on a first gate region;
a second gate contact on a second gate region;
a first source/drain contact;
a second source/drain contact; and
a diffusion break region between the first gate contact and the second gate contact, and between the first source/drain contact and the second source/drain contact, a first edge of the diffusion break region abutting an edge of the first gate contact and a second edge of the diffusion break region abutting an edge of the second gate contact;
wherein a top surface of the diffusion break region is co-planar with at least one of top surfaces of the first and second gate contacts and top surfaces of the first and second source/drain contacts.
19 . The semiconductor device of claim 18 , wherein a third edge of the diffusion break region abuts an edge of the first source/drain contact and a fourth edge of the diffusion break region abuts an edge of the second source/drain contact.
20 . The semiconductor device of claim 18 wherein a bottom surface of the diffusion break region is under at least one of a bottom surface of one or more of the first and second gate contacts and a bottom surface of one or more of the first and second source/drain contacts.