Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures
The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.
1. A structure comprising a single diffusion break (SDB) region comprising a plurality of shallow trench isolation (STI) regions partially filling trenches and a first stress fill material within a recess of a first STI region and a second stress fill material within a recess of a second STI region different from the first stress fill material, the first and second stress fill materials imparting a stress on a gate structure adjacent to the first and second STI regions.
2. The structure of claim 1 , wherein the first stress fill material or the second stress fill material comprises a liner and a fill material within the recess of the first STI region or the second STI region.
3. The structure of claim 1 , wherein the first stress fill material or the second stress fill material comprises a single material within the recess of the first STI region or the second STI region.
4. The structure of claim 2 , wherein the recess is approximately 20% to 60% of a depth of the first STI region or the second STI region.
5. The structure of claim 1 , wherein the first stress fill material exhibits a tensile stress on the gate structure or a compressive stress on the gate structure.
6. The structure of claim 1 , wherein the first stress fill material is an insulator material.
7. The structure of claim 1 , wherein:
the first stress fill material imparts a tensile stress; and
the second stress fill material imparts a compressive stress.
8. The structure of claim 1 , further comprising a double diffusion break (DDB) region comprising an additional STI region with a non-stress fill material.
9. The structure of claim 1 , further comprising a substrate that is a fin structure and the first STI region and the second STI region are etched in the fin structure, with the gate structure extending over the fin structure and adjacent to the first STI region and the second STI region.
10. The structure of claim 1 , wherein the first stress fill material comprises a liner within the recess of the first STI region and a fill material deposited over the liner.
11. The structure of claim 10 , further comprising a substrate that is a fin structure, wherein the first stress fill material and the second stress fill material are raised over the fin structure, the gate structure extends over the fin structure and wherein the liner is over an oxide fill of the at least one STI region.
12. A structure comprising:
a first single diffusion break (SDB) region comprising a trench and a first shallow trench isolation (STI) region in a bottom portion of the trench, and a first stress fill material within the trench and having opposing sides covered by the first STI region, the first stress fill material imparting a stress favorable to a SDB NFET device; and
a second SDB region comprising a second STI region with a second stress fill material that imparts a stress favorable to a SDB PFET device, wherein the first stress fill material is within a recces of the first STI region of the first SDB region, the second stress fill material being different from the first stress fill material and the first stress fill material is over an oxide fill within the recess.
13. The structure of claim 12 , wherein the first stress fill material for the SDB NFET device has a tensile stress component and the second stress fill material for the SDB PFET device has a compressive stress component.
14. The structure of claim 12 , wherein the first stress fill material and the second stress fill material include a liner and a fill material.
15. The structure of claim 12 , wherein the first stress fill material and the second stress fill material are within a recess of the respective first and second STI regions.
16. The structure of claim 15 , wherein the recess is approximately 20% to 60% of a depth of the respective first and second STI regions.
17. The structure of claim 12 , wherein the first and second stress material are a single material.
18. The structure of claim 12 , further comprising a double diffusion break (DDB) region comprising an additional STI region with a non-stress fill material.
19. The structure of claim 12 , wherein the first STI region for the first SDB region and the second STI region for the second SDB region are within a fin structure of semiconductor material.
20. The structure of claim 19 , wherein the SDB NFET device and the SDB PFET device extend over the fin structure, adjacent to the respective first and second STI regions.