IP Library › Granted Patent US 12,628,450
Granted Patent B2
US 12,628,450 · App. 18/084,728 · Granted May 12, 2026

Defect prevention methods for pixel-array substrates

Inventors: Qin Wang (San Jose, CA); Gang Chen (San Jose, CA)
Assignee: OmniVision Technologies, Inc.
H10F39/805H10F39/024H10F39/807H10F39/8063
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Quick Facts
Patent No.
US 12,628,450
App. No.
18/084,728
Granted
May 12, 2026
Kind
B2
Abstract

A method for preventing defects in a thin film deposited on a semiconductor substrate includes forming a plurality of trenches on a periphery-region of the semiconductor substrate to yield a trenched surface. The semiconductor substrate includes a pixel array; the periphery-region surrounds the pixel array. The trenched surface includes (i) a plurality of trench regions each forming a respective one of the plurality of trenches and (ii) between each pair of adjacent trenches, a respective one of a plurality of inter-trench surfaces. The method also includes depositing the thin film on the surface such that the thin film covers each inter-trench surface and conformally covers each trench region.

Claims (33)

1 . A method for preventing defects in a thin film deposited on a semiconductor substrate that includes a pixel array, the method comprising:

forming a plurality of trenches on a periphery-region of the semiconductor substrate to yield a trenched surface that includes (i) a plurality of trench regions each forming a respective one of the plurality of trenches and (ii) between each pair of adjacent trenches, a respective one of a plurality of inter-trench surfaces, the periphery-region surrounding the pixel array; and

depositing the thin film on the periphery-region such that the thin film covers each inter-trench surface and conformally covers each trench region;

the periphery-region comprising a conductive element, which is either a through-silicon via through the semiconductor substrate or a back-side ground contact on a surface of the semiconductor substrate;

said forming comprising forming the plurality of trenches such that the conductive element is between two adjacent trenches of the plurality of trenches.

2 . The method of claim 1 , forming the plurality of trenches comprising lithographically etching a surface of the periphery-region, the surface being part of a back surface of the semiconductor substrate.

3 . The method of claim 1 , further comprising:

annealing the thin film; and

filling each of the plurality of trenches with at least one of an oxide material and a metal.

4 . The method of claim 1 , in the step of forming, each trench of the plurality of trenches being perpendicular to and intersecting at least one other trench of the plurality of trenches, the plurality of trenches forming a grid.

5 . The method of claim 1 , the semiconductor substrate including a central-region surrounded by the periphery-region and, in the step of forming, the plurality of trenches including a plurality of central-region trenches each traversing both the periphery-region and the central-region and being located between either (i) a pair of adjacent pixel-rows of the pixel array and (ii) a pair of adjacent pixel-columns of the pixel array.

6 . The method of claim 1 , each inter-trench surface being a respective planar region of a back surface of the semiconductor substrate between two adjacent trenches of the plurality of trenches.

7 . The method of claim 1 , in the step of forming,

each trench of the plurality of trenches extending into the semiconductor substrate and having a depth, relative to a planar region of a back surface of the semiconductor substrate surrounding the trench, that is less than a thickness of the semiconductor substrate.

8 . The method of claim 7 , in said step of forming, the plurality of trenches including a plurality of first peripheral-trenches and a plurality of second peripheral-trenches each perpendicular to each of the plurality of first peripheral-trenches.

9 . The method of claim 8 , said step of forming resulting in the trenched surface including a trench grid structure, and further comprising filling each of the plurality of trenches with an insulating material.

10 . The method of claim 1 , in said step of depositing, the thin film being a passivation layer.

11 . The method of claim 10 , in said step of depositing, the passivation layer being formed of a high-material.

12 . A method for preventing defects in a thin film deposited on a semiconductor substrate that includes a pixel array, the method comprising:

forming a plurality of trenches on a periphery-region of the semiconductor substrate to yield a trenched surface that includes (i) a plurality of trench regions each forming a respective one of the plurality of trenches and (ii) between each pair of adjacent trenches, a respective one of a plurality of inter-trench surfaces, the periphery-region surrounding the pixel array;

filling each of the plurality of trenches with an insulating material; and

depositing the thin film on the periphery-region such that the thin film covers each inter-trench surface and conformally covers each trench region;

the periphery-region comprising a conductive element, which is either a through-silicon via through the semiconductor substrate or a back-side ground contact on a surface of the semiconductor substrate;

said forming comprising forming the plurality of trenches such that the conductive element is between two adjacent trenches of the plurality of trenches.

13 . The method of claim 12 , said forming comprising forming the plurality of trenches such that a distance between the conductive element and any adjacent trenches of the plurality of trenches exceeds a process margin.

14 . The method of claim 12 , said forming comprising forming the plurality of trenches such that one or more of the plurality of trenches is in part of the periphery-region located between a guard ring structure and the pixel array, wherein the guard ring structure surrounds the pixel array.

15 . The method of claim 14 , said forming comprising forming the plurality of trenches such that a distance between the guard ring structure and any adjacent trenches of the plurality of trenches exceeds a process margin.

16 . The method of claim 12 , in said step of depositing, the thin film being a passivation layer formed of a high-k material.

17 . The method of claim 12 , in the step of forming, each trench of the plurality of trenches being perpendicular to and intersecting at least one other trench of the plurality of trenches, the plurality of trenches forming a grid.

18 . The method of claim 12 , said forming comprising:

etching the plurality of trenches with a gas etchant containing fluorine such that the fluorine reaches another surface of the semiconductor substrate that is opposite to the surface of the semiconductor substrate.

19 . The method of claim 16 , after said depositing comprising:

annealing the thin film using a hydrogen annealing process to densify the thin film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2022
From: WANG, QIN; CHEN, GANG
To: OMNIVISION TECHNOLOGIES, INC.
Reel/Frame 062155/0716 →
Continuity (2)
Division 16905670 · Jun 18, 2020
Related Publication 20230122521A1 · Apr 20, 2023
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