Granted Patent B2

US 12,657,024 · App. 18/086,484 · Granted Jun 16, 2026

Inventors: Harold Carter Edwards (Campbell, CA); Stephen Anthony Bernard Jones (San Francisco, CA); Alexander Lev Minkin (Los Altos, CA); Olivier Giroux (Santa Clara, CA); Gokul Ramaswamy Hirisave Chandra Shekhara (Bangalore, IN); Aditya Avinash Atluri (Redmond, WA); Apoorv Parle (Santa Clara, CA); Ronny Meir Krashinsky (Portola Valley, CA); Alan Kaatz (Seattle, WA); Andrew Robert Kerr (Atlanta, GA); Jack H. Choquette (Palo Alto, CA)

Assignee: NVIDIA Corporation

G06T1/20G06F3/0625G06F3/0646G06F3/0659G06F3/0673G06F9/30047G06F9/3802G06F9/541G06F9/544G06F12/0811G06F12/0862G06T1/60G06F17/16G06F2212/608G06F2212/62

Abstract

Claims (23)

1 . A graphics processing unit (GPU), comprising: one or more circuits to perform a tensor prefetch instruction to cause one or more tensors to be transformed based, at least in part, on a parameter indicating a portion of a tensor which one or more image-to-column transformations are to be applied and stored into one or more GPU caches.

2 . The GPU of claim 1 , wherein the tensor prefetch instruction is to cause the one or more tensors to be stored by the GPU.

3 . The GPU of claim 1 , wherein the one or more GPU caches comprise a level two (L2) cache.

4 . The GPU of claim 1 , wherein the parameter comprises a tensor map data structure to use to transform the one or more tensors.

5 . The GPU of claim 4 , wherein the one or more tensors are to be transformed using one or more additional transformations according to the tensor map data structure.

6 . The GPU of claim 1 , wherein an input to the tensor prefetch instruction indicates a portion of a tensor to be transformed.

7 . The GPU of claim 1 , wherein an input to the tensor prefetch instruction comprises an offset to be used to transform the one or more tensors.

8 . A system, comprising: one or more processors to perform a tensor prefetch instruction to cause one or more tensors to be transformed based, at least in part, on a parameter indicating a portion of a tensor which one or more image-to-column transformations are to be applied and stored into one or more graphics processing unit (GPU) caches.

9 . The system of claim 8 , wherein the tensor prefetch instruction is to cause the one or more tensors to be transformed and stored asynchronously.

10 . The system of claim 8 , wherein the tensor prefetch instruction is to cause the one or more tensors to be stored by the one or more processors.

11 . The system of claim 8 , wherein the one or more GPU caches comprise a level two (L2) cache.

12 . The system of claim 8 , wherein the one or more tensors are to be transformed using one or more additional transformations according to a tensor map structure.

13 . The system of claim 8 , wherein an input to the tensor prefetch instruction indicates a memory location to be used to transform the one or more tensors.

14 . A method, comprising:

accessing a tensor prefetch instruction, comprising a tensor map indicating one or more image-to-column transformations that are to be applied to a portion of one or more tensors;

performing the tensor prefetch instruction to cause the one or more tensors to be transformed according to the tensor map; and

causing the transformed one or more tensors to be asynchronously stored into one or more graphics processing unit (GPU) caches.

15 . The method of claim 14 , wherein the tensor map comprises a tensor map data structure to use to transform the one or more tensors.

16 . The method of claim 15 , wherein performing the tensor prefetch instruction comprises performing one or more additional transformations according to the tensor map data structure.

17 . The method of claim 14 , wherein performing the tensor prefetch instruction comprises compiling the tensor prefetch instruction to obtain one or more instructions performable by the GPU.

18 . The method of claim 14 , wherein performing the tensor prefetch instruction comprises using a tensor map to obtain the one or more tensors.

19 . The method of claim 14 , wherein performing the tensor prefetch instruction comprises obtaining a portion of a tensor based, at least in part, on an input to the tensor prefetch instruction.

20 . A non-transitory computer-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least perform the method of claim 14 .

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (301)