Electrostatic discharge protection structure and chip
An electrostatic discharge protection structure and a chip are provided. The electrostatic discharge protection structure includes: a semiconductor substrate, an N-type well, a P-type well, a first N-type doped portion, a first P-type doped portion, a second P-type doped portion and a second N-type doped portion. The N-type well and the P-type well are located in the semiconductor substrate. The first N-type doped portion and the second P-type doped portion are located in the P-type well, and the first P-type doped portion and the second N-type doped portion are located in the N-well. The first N-type doped portion has a “T” shape structure, the first P-type doped portion has a “U” shape structure, and a part of the first N-type doped portion is located in a “U” shape opening of the first P-type doped portion.
1 . An electrostatic discharge protection structure, comprising:
a semiconductor substrate;
an N-type well located in the semiconductor substrate;
a P-type well located in the semiconductor substrate;
a first N-type doped portion located in the P-type well, wherein the first N-type doped portion comprises a first extension portion and a second extension portion that are connected to each other;
wherein an orthographic projection of the first extension portion on a target projection plane extends along a first direction, an orthographic projection of the second extension portion on the target projection plane extends along a second direction, the target projection plane is parallel to a plane where the semiconductor substrate is located, and the first direction intersects the second direction:
a first P-type doped portion located in the N-type well, wherein the first P-type doped portion comprises a third extension portion, a fourth extension portion, and a fifth extension portion connected between the third extension portion and the fourth extension portion;
wherein both an orthographic projection of the third extension portion on the target projection plane and an orthographic projection of the fourth extension portion on the target projection plane extend along the second direction, the orthographic projection of the second extension portion on the target projection plane is located between the orthographic projection of the third extension portion on the target projection plane and the orthographic projection of the fourth extension portion on the target projection plane, and an orthographic projection of the fifth extension portion on the target projection plane is located on a side of the orthographic projection of the second extension portion on the target projection plane away from the orthographic projection of the first extension portion on the target projection plane;
a second P-type doped portion located in the P-type well, wherein an orthographic projection of the second P-type doped portion on the target projection plane extends along the first direction, and is located on a side of an orthographic projection of the first N-type doped portion on the target projection plane away from an orthographic projection of the first P-type doped portion on the target projection plane; and
a second N-type doped portion located in the N-type well, wherein an orthographic projection of the second N-type doped portion on the target projection plane extends along the first direction, and is located on a side of the orthographic projection of the first P-type doped portion on the target projection plane away from the orthographic projection of the first N-type doped portion on the target projection plane;
wherein the second P-type doped portion is electrically connected to the second N-type doped portion.
2 . The electrostatic discharge protection structure of claim 1 , further comprising:
a third N-type doped portion located in the P-type well, wherein an orthographic projection of the third N-type doped portion on the target projection plane and the orthographic projection of the first N-type doped portion on the target projection plane are arranged at intervals in the first direction;
wherein the third N-type doped portion comprises a sixth extension portion and a seventh extension portion that are connected to each other, an orthographic projection of the sixth extension portion on the target projection plane extends along the first direction, and an orthographic projection of the seventh extension portion on the target projection plane extends along the second direction; and
a third P-type doped portion located in the N-type well, wherein an orthographic projection of the third P-type doped portion on the target projection plane and the orthographic projection of the first P-type doped portion on the target projection plane are arranged at intervals in the first direction;
wherein the third P-type doped portion comprises an eighth extension portion, a ninth extension portion, and a tenth extension portion connected between the eighth extension portion and the ninth extension portion, both an orthographic projection of the eighth extension portion on the target projection plane and an orthographic projection of the ninth extension portion on the target projection plane extend along the second direction, the orthographic projection of the seventh extension portion on the target projection plane is located between the orthographic projection of the eighth extension portion on the target projection plane and the orthographic projection of the ninth extension portion on the target projection plane, and an orthographic projection of the tenth extension portion on the target projection plane is located on a side of the orthographic projection of the seventh extension portion on the target projection plane away from the orthographic projection of the sixth extension portion on the target projection plane;
the orthographic projection of the second P-type doped portion on the target projection plane is located on a side of the orthographic projection of the third N-type doped portion on the target projection plane away from the orthographic projection of the third P-type doped portion on the target projection plane; and
the orthographic projection of the second N-type doped portion on the target projection plane is located on a side of the orthographic projection of the third P-type doped portion on the target projection plane away from the orthographic projection of the third N-type doped portion on the target projection plane.
3 . The electrostatic discharge protection structure of claim 2 , wherein a part of the first extension portion and at least part of the third extension portion are oppositely arranged in the second direction, and another part of the first extension portion and at least part of the fourth extension portion are oppositely arranged in the second direction; and
a part of the sixth extension portion and at least part of the eighth extension portion are oppositely arranged in the second direction, and another part of the sixth extension portion and at least part of the ninth extension portion are oppositely arranged in the second direction.
4 . The electrostatic discharge protection structure of claim 2 , wherein the P-type well comprises:
a first well region, wherein an orthographic projection of the first well region on the target projection plane extends along the first direction;
a second well region connected to the first well region, wherein an orthographic projection of the second well region on the target projection plane extends along the second direction; and
a third well region connected to the first well region, wherein an orthographic projection of the third well region on the target projection plane extends along the second direction, and the orthographic projection of the third well region on the target projection plane and the orthographic projection of the second well region on the target projection plane are located on a same side of the orthographic projection of the first well region on the target projection plane;
wherein the first extension portion, the sixth extension portion and the second P-type doped portion are located in the first well region, the second extension portion is located in the second well region, and the seventh extension portion is located in the third well region.
5 . The electrostatic discharge protection structure of claim 2 , wherein at least part of the first extension portion and a part of the second P-type doped portion are oppositely arranged in the second direction, and at least part of the sixth extension portion and another part of the second P-type doped portion are oppositely arranged in the second direction; and
at least part of the fifth extension portion and a part of the second N-type doped portion are oppositely arranged in the second direction, and at least part of the tenth extension portion and another part of the second N-type doped portion are oppositely arranged in the second direction.
6 . The electrostatic discharge protection structure of claim 1 , wherein an orthographic projection of the N-type well on the target projection plane surrounds an orthographic projection of the P-type well on the target projection plane;
wherein the semiconductor substrate is a P-type semiconductor substrate, and the electrostatic discharge protection structure further comprises:
an N-type deep well isolated between the semiconductor substrate and the P-type well.
7 . The electrostatic discharge protection structure of claim 1 , further comprising:
an annular doped portion, wherein an orthographic projection of the annular doped portion on the target projection plane surrounds an orthographic projection of the N-type well on the target projection plane and an orthographic projection of the P-type well on the target projection plane; and
a doping type of the annular doped portion and a doping type of the semiconductor substrate are identical.
8 . A chip, comprising the electrostatic discharge protection structure of claim 1 .
9 . The chip of claim 8 , further comprising a first terminal and a second terminal, wherein the first terminal is connected to the first N-type doped portion, and the second terminal is connected to the first P-type doped portion.
10 . The chip of claim 9 , further comprising a high level power supply terminal, a low level power supply terminal, and a signal transmission terminal, wherein
the first terminal is the high level power supply terminal, and the second terminal is the signal transmission terminal; or
the first terminal is the signal transmission terminal, and the second terminal is the low level power supply terminal; or
the first terminal is the high level power supply terminal, and the second terminal is the low level power supply terminal.
11 . The chip of claim 8 , further comprising a low level power supply terminal and a signal transmission terminal, wherein
in a case that the electrostatic discharge protection structure comprises a third P-type doped portion and a third N-type doped portion, the signal transmission terminal is connected to the first P-type doped portion and the third N-type doped portion, and the low level power supply terminal is connected to the first N-type doped portion and the third P-type doped portion.
12 . The chip of claim 11 , wherein the signal transmission terminal comprises a signal output terminal and a signal input terminal, the chip comprises a plurality of the electrostatic discharge protection structures, and the plurality of the electrostatic discharge protection structures comprises:
a first electrostatic discharge protection structure, wherein the first P-type doped portion and the third N-type doped portion of the first electrostatic discharge protection structure are connected to the signal input terminal, and the first N-type doped portion and the third P-type doped portion of the first electrostatic discharge protection structure are connected to the low level power supply terminal; and
a second electrostatic discharge protection structure, wherein the first P-type doped portion and the third N-type doped portion of the second electrostatic discharge protection structure are connected to the signal output terminal, and the first N-type doped portion and the third P-type doped portion of the second electrostatic discharge protection structure are connected to the low level power supply terminal.
13 . The chip of claim 8 , further comprising a high level power supply terminal, a low level power supply terminal, and a signal transmission terminal, wherein
in a case that the electrostatic discharge protection structure comprises a third P-type doped portion and a third N-type doped portion, the signal transmission terminal is connected to the first P-type doped portion and the third N-type doped portion, the high level power supply terminal is connected to the first N-type doped portion, and the low level power supply terminal is connected to the third P-type doped portion.
14 . The chip of claim 13 , wherein the signal transmission terminal comprises a signal output terminal and a signal input terminal, the chip comprises a plurality of the electrostatic discharge protection structures, and the plurality of the electrostatic discharge protection structures comprises:
a first electrostatic discharge protection structure, wherein the first P-type doped portion and the third N-type doped portion of the first electrostatic discharge protection structure are connected to the signal input terminal, the first N-type doped portion of the first electrostatic discharge protection structure is connected to the high level power supply terminal, and the third P-type doped portion of the first electrostatic discharge protection structure is connected to the low level power supply terminal; and
a second electrostatic discharge protection structure, wherein the first P-type doped portion and the third N-type doped portion of the second electrostatic discharge protection structure are connected to the signal output terminal, the first N-type doped portion of the second electrostatic discharge protection structure is connected to the high level power supply terminal, and the third P-type doped portion of the second electrostatic discharge protection structure is connected to the low level power supply terminal.
15 . The chip of claim 8 , wherein the chip is a dynamic random access memory or a static random access memory.