Semiconductor device
Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring configured to transmit a first potential,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring configured to transmit a second potential,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one electrode of the capacitor,
wherein a gate of the second transistor is electrically connected to the other electrode of the capacitor,
wherein the gate of the second transistor is electrically connected to a fourth wiring configured to transmit a signal,
wherein a gate of the third transistor is electrically connected to the first wiring,
wherein a gate of the fourth transistor is electrically connected to the fourth wiring,
wherein the fifth transistor is configured to control electrical continuity between the first wiring and the one electrode of the capacitor, and
wherein the signal transmitted from the fourth wiring is configured to control a potential of the gate of the fourth transistor and a potential of the gate of the second transistor.
2. The semiconductor device according to claim 1 , wherein the first potential is different from the second potential.
3. The semiconductor device according to claim 1 , wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor.
4. The semiconductor device according to claim 1 , wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fifth transistor.
5. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring configured to transmit a first potential,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring configured to transmit a second potential,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one electrode of the capacitor,
wherein a gate of the second transistor is electrically connected to the other electrode of the capacitor,
wherein the gate of the second transistor is electrically connected to a fourth wiring configured to transmit a signal,
wherein a gate of the third transistor is electrically connected to the first wiring,
wherein a gate of the fourth transistor is electrically connected to the fourth wiring,
wherein the fifth transistor is configured to control electrical continuity between the first wiring and the one electrode of the capacitor,
wherein the signal transmitted from the fourth wiring is configured to control a potential of the gate of the fourth transistor and a potential of the gate of the second transistor,
wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor, and
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fifth transistor.
6. The semiconductor device according to claim 5 , wherein the first potential is different from the second potential.
7. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring configured to transmit a first potential,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring configured to transmit a second potential,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one electrode of the capacitor,
wherein a gate of the second transistor is electrically connected to the other electrode of the capacitor,
wherein the gate of the second transistor is electrically connected to a fourth wiring configured to transmit a signal,
wherein a gate of the third transistor is electrically connected to the first wiring,
wherein a gate of the fourth transistor is electrically connected to the fourth wiring,
wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor, and
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fifth transistor.
8. The semiconductor device according to claim 7 , wherein the first potential is different from the second potential.