Memory system and method for operating memory system
The memory system may include a processor; a scratch pad memory connected to the processor through an internal bus, a memory controller connected to the processor through the internal bus, and configured to access a memory device through an external bus in response to a memory access request by the processor; and a hint managing module configured to manage a hint for selecting data to be overridden on the scratch pad memory from among data loaded in the memory device.
1 . A memory system comprising:
a processor;
a scratch pad memory connected to the processor through an internal bus;
a memory controller connected to the processor through the internal bus, and configured to access a memory device through an external bus in response to a memory access request by the processor; and
a hint managing circuit configured to manage a hint for selecting data to be duplicated in the scratch pad memory from among data loaded in the memory device, wherein the hint includes information characterizing how to select at least one code section, among a plurality of code sections defined in the memory device, to be duplicated in the scratch pad memory based on expected execution characteristics of the at least one code section.
2 . The memory system of claim 1 , wherein the hint managing circuit includes a hint decision circuit configured to analyze the plurality of code sections defined in the memory device, and to provide the information characterizing how to select the at least one code section as the hint.
3 . The memory system of claim 2 , wherein the hint managing circuit includes a code section decision circuit configured to decide a code section to be duplicated in the scratch pad memory based on the hint.
4 . The memory system of claim 3 , wherein the hint managing circuit includes an address identification circuit configured to identify a physical address on the decided code section.
5 . The memory system of claim 4 , wherein the hint managing circuit includes a scratch pad memory mapping circuit configured to duplicate at least one instruction corresponding to the decided code section to the scratch pad memory from the memory device by using the identified physical address.
6 . The memory system of claim 5 , wherein the scratch pad memory mapping circuit is configured to map so that the scratch pad memory indicates a code section in the memory device corresponding to the decided code section.
7 . The memory system of claim 1 , wherein the processor is configured to access data duplicated in the scratch pad memory without an intervention of the memory controller.
8 . The memory system of claim 1 , wherein the hint is set to select data of which a compulsory cache miss is predicted to be generated beyond a predetermined reference from among the data loaded in the memory device.
9 . The memory system of claim 1 , wherein the hint is set to select data of which continuity of a code address is predicted to be given below a predetermined reference from among the data loaded in the memory device.
10 . The memory system of claim 1 , wherein the hint is set to select data of which spatial locality is predicted to be given below a predetermined reference from among the data loaded in the memory device.
11 . The memory system of claim 1 , wherein the hint indicates that the at least one code section has a higher execution rate in the scratch pad memory than in a cache.
12 . A memory system comprising:
a memory device including a code section in a predetermined address;
a scratch pad memory configured to receive and store a copy of at least a portion of the code section from the memory device;
a processor configured to prefetch an instruction of the copy stored in the scratch pad memory so as to access the code section according to the predetermined address; and
a hint managing circuit configured to manage a hint for selecting data to be duplicated in the scratch pad memory from among data loaded in the memory device, wherein the hint includes information characterizing how to select at least one code section, among a plurality of code sections defined in the memory device, to be duplicated in the scratch pad memory based on expected execution characteristics of the at least one code section.
13 . The memory system of claim 12 , further comprising
a cache,
wherein the code section included in the memory device includes a first code section and a second code section,
the scratch pad memory receives and stores a copy of the first code section,
the cache receives and stores a copy of the second code section, and
the processor accesses the scratch pad memory to access the first code section, and accesses the cache to access the second code section.
14 . The memory system of claim 13 , wherein
the code section included in the memory device further includes a third code section, and
the processor accesses the memory device to access the third code section.
15 . The memory system of claim 13 , wherein
the processor is connected to the scratch pad memory and the cache through an internal bus, and
the processor is connected to the memory device through an external bus.
16 . A method for operating a memory system comprising:
analyzing a plurality of code sections defined in a memory device, and providing a hint, wherein the hint includes information characterizing how to select at least one code section, among the plurality of code sections defined in the memory device, to be duplicated in a scratch pad memory based on expected execution characteristics of the at least one code section;
deciding a code section to be duplicated in the scratch pad memory based on the hint;
identifying a physical address on the decided code section;
duplicating at least one instruction corresponding to the decided code section to the scratch pad memory from the memory device by using the identified physical address; and
mapping so that the scratch pad memory indicates a code section in the memory device corresponding to the decided code section.
17 . The method of claim 16 , further comprising
prefetching the at least one instruction stored in the scratch pad memory in order for a processor to access the decided code section.
18 . The method of claim 16 , wherein the hint is set to select data of which a compulsory cache miss is predicted to be generated for more than a predetermined reference from among data loaded in the memory device.
19 . The method of claim 16 , wherein the hint is set to select data of which continuity of a code address is predicted to be given below a predetermined reference from among data loaded in the memory device.
20 . The method of claim 16 , wherein the hint is set to select data of which spatial locality is predicted to be given below a predetermined reference from among data loaded in the memory device.