Shadow access port method and apparatus
The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
1. An electrical device comprising;
(a) device terminals including functional input terminals, functional output terminals, a TDI input terminal, a TMS input terminal, a TCK input terminal, and a TDO output terminal;
(b) functional circuitry coupled to the functional input terminals and coupled to the functional output terminals;
(c) a first access port circuit having a data input coupled to the TDI input terminal, a control input coupled to the TMS input terminal, a clock input coupled to the TCK input terminal, a data output, and a first enable output;
(d) a second access port circuit having a data input coupled to the TDI input terminal, a control input coupled to the TMS input terminal, a clock input coupled to the TCK input terminal, a data output, and a second enable output; and
(e) an output control circuit having a first data input coupled to the data output of the first access port circuit, a second data input coupled to the data output of the second access port circuit, a first enable input coupled the first enable output, a second enable input coupled to the second enable output and a data output coupled to the TDO output terminal.
2. The electrical device of claim 1 , wherein the first access port circuit operates according to IEEE Standard 1149.1.
3. The electrical device of claim 1 , wherein the second access port circuit operates apart from IEEE Standard 1149.1.
4. The electrical device of claim 1 , further comprising test circuitry associated with the functional circuitry, wherein the first access port circuit operates to access the test circuitry.
5. The electrical device of claim 1 , further comprising:
debug circuitry associated with the functional circuitry; or
trace circuitry associated with the functional circuitry,
wherein the second access port circuit operates to access the debug circuitry or the trace circuitry.
6. The electrical device of claim 1 , wherein the electrical device is an integrated circuit.
7. The electrical device of claim 1 , wherein the electrical device is a core within an integrated circuit.
8. The electrical device of claim 1 , wherein the first access port circuit further includes:
a data register coupled to the TDI input terminal; and
an instruction register coupled to the TDI input terminal.
9. The electrical device of claim 8 , wherein the first access port circuit further includes a multiplexer circuit configured to:
selectively couple the data register to the TDO output terminal; and
selectively couple the instruction register to the TDO output terminal.
10. The electrical device of claim 1 , wherein the second access port circuit further includes:
a data register coupled to the TDI input terminal; and
an instruction register coupled to the TDI input terminal.
11. The electrical device of claim 10 , wherein the second access port circuit further includes a multiplexer circuit configured to:
selectively couple the data register to the TDO output terminal; and
selectively couple the instruction register to the TDO output terminal.
12. The electrical device of claim 1 ,
wherein the first access port circuit includes a first state machine configured to change states upon a rising edge of a clock signal at the TCK input terminal, and
wherein the second access port circuit includes a second state machine configured to change states upon a falling edge of the clock signal at the TCK input terminal.
13. The electrical device of claim 1 ,
wherein the first access port circuit is configured to change states upon a rising edge of a clock signal at the TCK input terminal, and
wherein the second access port circuit is configured to change states upon a falling edge of the clock signal at the TCK input terminal.
14. The electrical device of claim 1 ,
wherein the first access port circuit is configured to change states upon a falling edge of a clock signal at the TCK input terminal, and
wherein the second access port circuit is configured to change states upon a rising edge of the clock signal at the TCK input terminal.
15. A device comprising:
a test data in (TDI) input terminal;
a test mode select (TMS) input terminal;
a test clock (TCK) input terminal;
a test data out (TDO) output terminal;
a first access port circuit configured to operate according to Institute of Electrical and Electronics Engineers (IEEE) standard 1149.1, wherein the first access port circuit includes:
a data input coupled to the TDI input terminal;
a control input coupled to the TMS input terminal;
a clock input coupled to the TCK input terminal;
a data output; and
a first enable output;
a second access port circuit configured to operate apart from the IEEE standard 1149.1, wherein the first access port circuit includes:
a data input coupled to the TDI input terminal;
a control input coupled to the TMS input terminal;
a clock input coupled to the TCK input terminal;
a data output; and
a second enable output; and
an output control circuit including:
a first data input coupled to the data output of the first access port circuit;
a second data input coupled to the data output of the second access port circuit;
a first enable input coupled the first enable output;
a second enable input coupled to the second enable output; and
a data output coupled to the TDO output terminal.
16. The device of claim 15 , further comprising test circuitry,
wherein the first access port circuit is configured to operate to access the test circuitry.
17. The device of claim 15 , further comprising debug circuitry associated,
wherein the second access port circuit is configured to operate to access the debug circuitry.
18. The device of claim 15 , further comprising trace circuitry,
wherein the second access port circuit is configured to operate to access the trace circuitry.
19. The device of claim 15 , wherein the second access port circuit further includes:
a data register coupled to the TDI input terminal; and
an instruction register coupled to the TDI input terminal.
20. The device of claim 19 , wherein the second access port circuit further includes a multiplexer circuit configured to:
selectively couple the data register to the TDO output terminal; and
selectively couple the instruction register to the TDO output terminal.