Static random access memory and method for fabricating the same
A method for fabricating a static random access memory (SRAM) includes the steps of forming a first fin-shaped structure for a first pull-down (PD) transistor on a substrate, forming a second fin-shaped structure for a second PD transistor on the substrate, forming a third fin-shaped structure for a first pass gate (PG) transistor on the substrate, and forming a fourth fin-shaped structure for a second PG transistor on the substrate. Preferably, the first fin-shaped structure and the second fin-shaped structure include a first recess therebetween and the third fin-shaped structure and the fourth fin-shaped structure include no recess therebetween.
1. A method for fabricating a static random access memory (SRAM), comprising:
forming a first fin-shaped structure for a first pull-down (PD) transistor on a substrate;
forming a second fin-shaped structure for a second PD transistor on the substrate, wherein the first fin-shaped structure and the second fin-shaped structure comprise a first recess therebetween;
forming a third fin-shaped structure for a first pass gate (PG) transistor on the substrate; and
forming a fourth fin-shaped structure for a second PG transistor on the substrate, wherein the third fin-shaped structure and the fourth fin-shaped structure comprise no recess therebetween.
2. The method of claim 1 , wherein the first fin-shaped structure and the second fin-shaped structure comprise a second recess therebetween.
3. The method of claim 2 , further comprising:
forming a fifth fin-shaped structure for a first pull-up (PU) transistor on the substrate; and
forming a sixth fin-shaped structure for a second PU transistor on the substrate, wherein the fifth fin-shaped structure and the sixth fin-shaped structure comprise a third recess therebetween.
4. The method of claim 3 , wherein the second fin-shaped structure and the fifth fin-shaped structure comprise a fourth recess therebetween.
5. The method of claim 4 , wherein third fin-shaped structure and the sixth fin-shaped structure comprise a fifth recess therebetween.
6. The method of claim 5 , further comprising:
performing a sidewall image transfer (SIT) process to remove the substrate for forming the first fin-shaped structure, the second fin-shaped structure, and a first dummy fin-shaped structure and a second dummy fin-shaped structure between the first fin-shaped structure and the second fin-shaped structure.
7. The method of claim 6 , further comprising:
performing the SIT process to remove the substrate for forming the third fin-shaped structure, the fourth fin-shaped structure, the fifth fin-shaped structure, the sixth fin-shaped structure, a third dummy fin-shaped structure between the fifth fin-shaped structure and the sixth fin-shaped structure, a fourth dummy fin-shaped structure between the second fin-shaped structure and the fifth fin-shaped structure, and a fifth dummy fin-shaped structure between the third fin-shaped structure and the sixth fin-shaped structure.
8. The method of claim 7 , further comprising:
performing a removal process to remove the first dummy fin-shaped structure, the second dummy fin-shaped structure, the third dummy fin-shaped structure, the fourth dummy fin-shaped structure, and the fifth dummy fin-shaped structure for forming the first recess, the second recess, the third recess, the fourth recess, and the fifth recess.
9. The method of claim 1 , wherein a width of the first fin-shaped structure is equal to a width of the second fin-shaped structure.
10. The method of claim 1 , wherein a width of the third fin-shaped structure is less than the width of the first fin-shaped structure.
11. A static random access memory (SRAM), comprising:
a first fin-shaped structure for a first pull-down (PD) transistor on a substrate;
a second fin-shaped structure for a second PD transistor on the substrate, wherein the first fin-shaped structure and the second fin-shaped structure comprise a first recess therebetween;
a third fin-shaped structure for a first pass gate (PG) transistor on the substrate; and
a fourth fin-shaped structure for a second PG transistor on the substrate, wherein the third fin-shaped structure and the fourth fin-shaped structure comprise no recess therebetween.
12. The SRAM of claim 11 , further comprising a second recess between the first fin-shaped structure and the second fin-shaped structure.
13. The SRAM of claim 12 , further comprising:
a fifth fin-shaped structure for a first pull-up (PU) transistor on the substrate; and
a sixth fin-shaped structure for a second PU transistor on the substrate, wherein the fifth fin-shaped structure and the sixth fin-shaped structure comprise a third recess therebetween.
14. The SRAM of claim 13 further comprising a fourth recess between the second fin-shaped structure and the fifth fin-shaped structure.
15. The SRAM of claim 14 , further comprising a fifth recess between the third fin-shaped structure and the sixth fin-shaped structure.
16. The SRAM of claim 11 , wherein a width of the first fin-shaped structure is equal to a width of the second fin-shaped structure.
17. The SRAM of claim 11 , wherein a width of the third fin-shaped structure is less than the width of the first fin-shaped structure.