SRAM bit cells formed with dummy structures
Structures including static random access memory bit cells and methods of forming a structure including static random access memory bit cells. A first bit cell includes a first plurality of semiconductor fins, and a second bit cell includes a second plurality of semiconductor fins. A deep trench isolation region is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell.
1. A method of forming a structure for a static random access memory, the method comprising:
forming a first plurality of semiconductor fins of a first bit cell;
forming a second plurality of semiconductor fins of a second bit cell;
forming a third plurality of semiconductor fins laterally positioned between the first plurality of semiconductor fins and the second plurality of semiconductor fins; and
forming a first deep trench isolation region that is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell,
wherein the first deep trench isolation region is formed in a first trench, and the third plurality of semiconductor fins are removed when the first trench is patterned.
2. The method of claim 1 wherein the first plurality of semiconductor fins define a six-transistor portion of the first bit cell, and further comprising:
forming a fourth plurality of semiconductor fins of the first bit cell; and
forming a second deep trench isolation region positioned between the first plurality of semiconductor fins and the fourth plurality of semiconductor fins,
wherein the fourth plurality of semiconductor fins define a read port of the first bit cell.
3. The method of claim 2 wherein the first deep trench isolation region and the second deep trench isolation region are concurrently formed.
4. The method of claim 1 wherein the first deep trench isolation region includes a portion that is arranged below a top surface of a substrate.
5. The method of claim 4 wherein the first plurality of semiconductor fins and the second plurality of semiconductor fins project away from the top surface of the substrate, and further comprising:
forming shallow trench isolation that surrounds the first plurality of semiconductor fins and the second plurality of semiconductor fins,
wherein the shallow trench isolation is comprised of a dielectric material, and the shallow trench isolation is positioned over the top surface of the substrate.
6. The method of claim 1 wherein the first plurality of semiconductor fins define a first six-transistor portion of the first bit cell, and the second plurality of semiconductor fins define a second six-transistor portion of the second bit cell.
7. The method of claim 1 wherein the first plurality of semiconductor fins have a first spacing, the second plurality of semiconductor fins have a second spacing, the first deep trench isolation region is laterally positioned in a break region between one of the first plurality of semiconductor fins and one of the second plurality of semiconductor fins, and the one of the first plurality of semiconductor fins and the one of the second plurality of semiconductor fins are separated by a distance that is greater than either the first spacing or the second spacing.
8. The method of claim 1 wherein the first plurality of semiconductor fins define a first six-transistor portion of the first bit cell, and the second plurality of semiconductor fins define a second six-transistor portion of the second bit cell.
9. The method of claim 8 wherein the first plurality of semiconductor fins define a six-transistor portion of the first bit cell, and further comprising:
forming a fourth plurality of semiconductor fins of the first bit cell,
wherein the fourth plurality of semiconductor fins define a read port of the first bit cell.
10. The method of claim 9 further comprising:
forming a second deep trench isolation positioned between the first plurality of semiconductor fins and the fourth plurality of semiconductor fins.
11. The method of claim 1 wherein the first plurality of semiconductor fins, the second plurality of semiconductor fins, and the third plurality of semiconductor fins are concurrently formed by an etching process.
12. The method of claim 1 wherein the first plurality of semiconductor fins, the second plurality of semiconductor fins, and the third plurality of semiconductor fins are concurrently formed by a self-aligned double patterning process.
13. The method of claim 1 wherein the first plurality of semiconductor fins and the second plurality of semiconductor fins project from a top surface of a semiconductor substrate, and further comprising:
forming a dielectric layer that surrounds the first plurality of semiconductor fins and the second plurality of semiconductor fins,
wherein the first deep trench isolation region includes a portion located in the semiconductor substrate below an interface between the dielectric layer and the top surface of the semiconductor substrate.
14. The method of claim 1 wherein forming the first deep trench isolation region that is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell comprises:
depositing a dielectric material in the first trench; and
planarizing the dielectric material to define the first deep trench isolation region.
15. The method of claim 14 wherein the dielectric material comprises silicon dioxide.
16. The method of claim 1 wherein the first plurality of semiconductor fins, the second plurality of semiconductor fins, and the third plurality of semiconductor fins are comprised of a single-crystal semiconductor material.
17. The method of claim 1 wherein the first plurality of semiconductor fins, the second plurality of semiconductor fins, and the third plurality of semiconductor fins are comprised of single-crystal silicon.