Semiconductor package and method of fabricating the same
A semiconductor package including a substrate comprising a plurality of vias; a chip stack on the substrate; and a mold layer on the substrate and on at least a portion of the chip stack. The chip stack includes a first semiconductor chip; second semiconductor chips stacked on the first semiconductor chip; a third semiconductor chip on the uppermost one of the second semiconductor chips; and non-conductive layers between the first semiconductor chip and the second semiconductor chips. A first chip pad of the first semiconductor chip is bonded to a substrate pad of the substrate. A second chip pad of the uppermost one of the second semiconductor chips is bonded to a third chip pad of the third semiconductor chip. Each of the second semiconductor chips is electrically connected to another of the second semiconductor chips or the first semiconductor chip.
1 . A semiconductor package, comprising:
a substrate comprising a plurality of vias;
a chip stack on the substrate; and
a mold layer on the substrate and on at least a portion of the chip stack,
wherein the chip stack comprises:
a first semiconductor chip;
second semiconductor chips stacked on the first semiconductor chip;
a third semiconductor chip on an uppermost one of the second semiconductor chips; and
non-conductive layers, wherein one of the non-conductive layers is between the first semiconductor chip and a lowermost one of the second semiconductor chips, and at least one other of the non-conductive layers is between the second semiconductor chips,
wherein a first chip pad of the first semiconductor chip is bonded to a substrate pad of the substrate,
wherein the first chip pad and the substrate pad each comprise the same metallic material and form a first single structure or layer,
wherein a second chip pad of the uppermost one of the second semiconductor chips is bonded to a third chip pad of the third semiconductor chip,
wherein the second chip pad and the third chip pad each comprise the same metallic material and form a second single structure or layer, and
wherein each of the second semiconductor chips is electrically connected to another of the second semiconductor chips or the first semiconductor chip using connection terminals on a bottom surface of each of the second semiconductor chips.
2 . The semiconductor package of claim 1 , wherein the non-conductive layers are disposed on the connection terminals, between the first semiconductor chip and the second semiconductor chips.
3 . The semiconductor package of claim 1 , wherein the non-conductive layers protrude to a region on a side surface of the chip stack, and
the non-conductive layers are spaced apart from the substrate and the third semiconductor chip.
4 . The semiconductor package of claim 1 , wherein a bottom surface of the first semiconductor chip is in direct contact with a top surface of the substrate, and
wherein a bottom surface of the third semiconductor chip is in direct contact with a top surface of the uppermost one of the second semiconductor chips.
5 . The semiconductor package of claim 1 , wherein the connection terminals comprise at least one of solder balls or solder bumps on the bottom surface of the second semiconductor chips.
6 . The semiconductor package of claim 1 , further comprising fourth semiconductor chips between the first semiconductor chip and the third semiconductor chip,
wherein each of the fourth semiconductor chips is provided on a top surface of a corresponding one of the second semiconductor chips,
wherein the semiconductor package further comprises chip structures that each comprise one of the second semiconductor chips and one of the fourth semiconductor chips, and
wherein the second semiconductor chips and the fourth semiconductor chips constituting each of the chip structures are in contact with each other.
7 . The semiconductor package of claim 6 , wherein, in the chip structures, the second semiconductor chips have active surfaces facing the substrate, and the fourth semiconductor chips have active surfaces facing the substrate.
8 . The semiconductor package of claim 6 , wherein, in the chip structures, the second semiconductor chips have active surfaces facing the third semiconductor chip, and the fourth semiconductor chips have active surfaces facing the substrate.
9 . The semiconductor package of claim 6 , wherein each of the chip structures is electrically connected to another one of the chip structures using the connection terminals on the bottom surfaces of the second semiconductor chips.
10 . The semiconductor package of claim 1 , wherein widths of the non-conductive layers increase as a distance from the substrate decreases.
11 . A semiconductor package, comprising:
a semiconductor substrate;
a chip stack on the semiconductor substrate; and
a mold layer on the semiconductor substrate and the chip stack,
wherein the chip stack comprises:
a first semiconductor chip on the semiconductor substrate;
chip structures stacked on the first semiconductor chip; and
non-conductive layers between the first semiconductor chip and the chip structures,
wherein each of the chip structures comprises:
a second semiconductor chip;
a third semiconductor chip on the second semiconductor chip; and
first connection terminals on a bottom surface of the second semiconductor chip,
wherein a bottom surface of the first semiconductor chip is in direct contact with a top surface of the semiconductor substrate,
wherein, in the chip structures, a bottom surface of the third semiconductor chip is in direct contact with a top surface of the second semiconductor chip,
wherein the non-conductive layers are provided on the first connection terminals,
wherein one of the non-conductive layers is between the first semiconductor chip and a lowermost one of the chip structures, and at least one other of the non-conductive layers is between the chip structures, and
wherein the non-conductive layers are spaced apart from the semiconductor substrate.
12 . The semiconductor package of claim 11 , wherein the non-conductive layers are spaced apart from the third semiconductor chip in an uppermost one of the chip structures.
13 . The semiconductor package of claim 11 , wherein a first chip pad of the first semiconductor chip is bonded to a substrate pad of the semiconductor substrate, and
the first chip pad and the substrate pad each comprise the same metallic material and form a single structure or layer.
14 . The semiconductor package of claim 11 , wherein, in the chip structures, a second chip pad of the second semiconductor chip is bonded to a third chip pad of the third semiconductor chip, and the second chip pad and the third chip pad each comprise the same metallic material and form a single structure or layer.
15 . The semiconductor package of claim 11 , wherein the non-conductive layers protrude to a region on a side surface of the chip stack, and
widths of the non-conductive layers increase as a distance from the semiconductor substrate decreases.
16 . The semiconductor package of claim 11 , wherein the first connection terminals comprise at least one of solder balls or solder bumps on the bottom surface of the second semiconductor chip.
17 . The semiconductor package of claim 11 , wherein, in each of the chip structures, an active surface of the second semiconductor chip and an active surface of the third semiconductor chip face the semiconductor substrate, and the active surface of the third semiconductor chip contacts an inactive surface of the second semiconductor chip.
18 . The semiconductor package of claim 11 , wherein, in each of the chip structures, an active surface of the second semiconductor chip and an active surface of the third semiconductor chip face each other, and the active surface of the third semiconductor chip and the active surface of the second semiconductor chip contact each other.
19 . The semiconductor package of claim 11 , wherein each of the chip structures further comprises a fourth semiconductor chip on the third semiconductor chip, and
wherein, in the chip structures, a bottom surface of the fourth semiconductor chip is in direct contact with a top surface of the third semiconductor chip.
20 . A semiconductor package, comprising:
a semiconductor substrate comprising a substrate pad;
a first semiconductor chip on the semiconductor substrate, the first semiconductor chip comprising a first chip pad bonded to the substrate pad of the semiconductor substrate, the first chip pad and the substrate pad each comprising the same metallic material and forming a single structure or layer;
second semiconductor chips stacked on the first semiconductor chip, wherein a lowermost one of the second semiconductor chips is electrically connected to the first semiconductor chip using connection terminals provided on a bottom surface of the lowermost one of the second semiconductor chips;
non-conductive layers on bottom surfaces of the second semiconductor chips, wherein a first one of the non-conductive layers is between the lowermost one of the second semiconductor chips and the first semiconductor chip, and a second one of the non-conductive layers is between two of the second semiconductor chips;
a third semiconductor chip on an uppermost one of the second semiconductor chips, the uppermost one of the second semiconductor chips and the third semiconductor chip comprising a second chip pad and a third chip pad, respectively, wherein the second chip pad and the third chip pad each comprise the same metallic material and are bonded to each other and form a single structure or layer; and
a mold layer on the semiconductor substrate and the first semiconductor chip, the second semiconductor chips, and the third semiconductor chip,
wherein the non-conductive layers are spaced apart from the semiconductor substrate and the third semiconductor chip,
wherein the first one of the non-conductive layers protrudes a first distance beyond a side surface of the lowermost one of the second semiconductor chips, and
wherein the second one of the non-conductive layers protrudes a second distance beyond side surfaces of the two of the second semiconductor chips, the second distance being less than the first distance.