Selective ILD deposition for fully aligned via with airgap
A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
1. A method comprising:
forming trenches within an insulating layer disposed over a semiconductor substrate;
filling the trenches with conductive material to form conductive regions;
selectively forming first dielectric regions on a pattern over exposed top surfaces of the insulating layer;
forming a mask over the semiconductor substrate and removing the first dielectric regions in areas not covered by the mask;
depositing an inter-layer dielectric over remaining first dielectric regions, the conductive regions, and the insulating layer; and
etching a portion of the inter-layer dielectric between two of the remaining first dielectric regions to form a self-aligned via.
2. The method of claim 1 , further comprising:
after removing the first dielectric regions in the areas not covered by the mask, etching exposed regions of the insulating layer disposed between adjacent conductive regions.
3. The method of claim 2 , further comprising,
after etching the exposed regions of the insulating layer disposed between the adjacent conductive regions, depositing the inter-layer dielectric to form at least one airgap between the adjacent conductive regions.
4. The method of claim 3 , further comprising:
after etching the exposed regions of the insulating layer disposed between the adjacent conductive regions, and before depositing the inter-layer dielectric, depositing a dielectric cap on (i) the remaining first dielectric regions, (ii) the conductive regions, and (iii) exposed portions of the insulating layer.
5. The method of claim 4 , further comprising,
after depositing the dielectric cap, depositing the inter-layer dielectric to form at least one airgap between the adjacent conductive regions.
6. The method of claim 4 , wherein the dielectric cap is conformal.
7. The method of claim 4 , wherein the dielectric cap comprises Si and C.
8. The method of claim 4 , wherein the dielectric cap comprises Si and N.
9. The method of claim 4 , wherein the dielectric cap comprises Si, C, and N.
10. The method of claim 4 , wherein the dielectric cap comprises Si, C, B, and N.
11. The method of claim 4 , wherein the dielectric cap comprises multilayers of Si, and one or more of C, B, and N.
12. The method of claim 4 , wherein the dielectric cap lines a portion of the self-aligned via.
13. The method of claim 1 , further comprising:
prior to forming the mask, forming second dielectric regions of the conductive regions and between the first dielectric regions.
14. The method of claim 13 , further comprising:
subsequent to removing the first dielectric regions in the areas not covered by the mask, damaging exposed regions of the insulating layer.
15. The method of claim 14 , wherein damaging the exposed regions of the insulating layer comprises ashing the exposed regions of the insulating layer.
16. The method of claim 13 , further comprising:
prior to depositing the inter-layer dielectric, removing the second dielectric regions.
17. The method of claim 1 , wherein the first dielectric regions comprise Si and O.
18. The method of claim 1 , wherein the first dielectric regions comprise Si, O, and N.
19. The method of claim 1 , wherein the first dielectric regions comprise Si, O, and C.
20. The method of claim 1 , wherein the first dielectric regions comprise Si, O, C, and N.