IP Library › Granted Patent US 12,347,484
Granted Patent B2
US 12,347,484 · App. 18/141,090 · Granted Jul 1, 2025

Memory device of non-volatile memory cells

Inventors: Hieu Van Tran (San Jose, CA); Nhan Do (Saratoga, CA); Farnood Merrikh Bayat (Goleta, CA); Xinjie Guo (Goleta, CA); Dmitri Strukov (Goleta, CA); Vipin Tiwari (Dublin, CA); Mark Reiten (Alamo, CA)
Assignees: Silicon Storage Technology, Inc.; The Regents of the University of California
G11C11/54G06F3/061G06F3/0655G06F3/0688G06N3/04G06N3/045G06N3/063G11C16/08G11C16/12G11C16/16G11C16/3436G11C29/38
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Quick Facts
Patent No.
US 12,347,484
App. No.
18/141,090
Granted
Jul 1, 2025
Kind
B2
Abstract

A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.

Claims (74)

1. A memory device, comprising:

a plurality of non-volatile memory cells arranged in rows and columns, having source regions arranged in rows and columns, and drain regions arranged in rows and columns, wherein respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other;

respective ones of the plurality of non-volatile memory cells comprise:

a channel region extending between one of the source regions and one of the drain regions,

a floating gate disposed over and insulated from a first portion of the channel region, and

a first non-floating gate disposed over and insulated from a second portion of the channel region;

a plurality of first lines, wherein respective ones of the plurality of first lines electrically connect together the source regions in one of the rows of the source regions and are physically isolated from the source regions in other rows of the source regions;

a plurality of second lines, wherein respective ones of the plurality of second lines electrically connect together the first drain regions of one of the columns of drain regions and are physically isolated from the second drain regions of the one column of drain regions;

a plurality of third lines, wherein respective ones of the plurality of third lines electrically connect together the second drain regions of one of the columns of drain regions and are physically isolated from the first drain regions of the one column of drain regions;

a plurality of fourth lines, wherein respective ones of the plurality of fourth lines electrically connect together the first non-floating gates of odd row memory cells in one of the columns of the memory cells and are physically isolated from the first non-floating gates of even row memory cells in the one column of the memory cells; and

a plurality of fifth lines, wherein respective ones of the plurality of fifth lines electrically connect together the first non-floating gates of even row memory cells in one of the columns of the memory cells and are physically isolated from the first non-floating gates of odd row memory cells in the one column of the memory cells.

2. The memory device of claim 1 , wherein for respective ones of the columns of drain regions:

the second line is physically isolated from the drain regions in other columns of the drain regions; and

the third line is physically isolated from the drain regions in other columns of the drain regions.

3. The memory device of claim 1 , wherein for respective ones of the columns of the memory cells:

the fourth line is physically isolated from the first non-floating gates in other columns of the memory cells; and

the fifth line is physically isolated from the first non-floating gates in other columns of the memory cells.

4. The memory device of claim 1 , wherein respective ones of the plurality of non-volatile memory cells comprise a second non-floating gate disposed over and insulated from the floating gate, the memory device comprising:

a plurality of sixth lines, wherein respective ones of the plurality of sixth lines electrically connect together the second non-floating gates in one of the rows of the memory cells.

5. The memory device of claim 1 , wherein respective ones of the plurality of non-volatile memory cells comprise a second non-floating gate disposed over and insulated from the source region, the memory device further comprising:

a plurality of sixth lines, wherein respective ones of the plurality of sixth lines electrically connect together the second non-floating gates in one of the columns of the memory cells.

6. The memory device of claim 1 , wherein respective ones of the plurality of non-volatile memory cells comprise a second non-floating gate disposed over and insulated from the floating gate and a third non-floating gate disposed over and insulated from the source region, the memory device comprising:

a plurality of sixth lines, wherein respective ones of the plurality of sixth lines electrically connect together the second non-floating gates in one of the rows of the memory cells; and

a plurality of seventh lines, wherein respective ones of the plurality of seventh lines electrically connect together the third non-floating gates in one of the columns of the memory cells.

7. The memory device of claim 1 , wherein respective ones of the plurality of non-volatile memory cells comprise a second non-floating gate disposed over and insulated from the floating gate, the memory device comprising:

a plurality of sixth lines, wherein respective ones of the plurality of sixth lines electrically connect together the second non-floating gates of odd row memory cells in one of the columns of the memory cells; and

a plurality of seventh lines, wherein respective ones of the plurality of seventh lines electrically connect together the second non-floating gates of even row memory cells in one of the columns of the memory cells.

8. The memory device of claim 1 , wherein respective ones of the plurality of non-volatile memory cells comprise a second non-floating gate disposed over and insulated from the source region, the memory device comprising:

a plurality of sixth lines, wherein respective ones of the plurality of sixth lines electrically connect together the second non-floating gates in one of the rows of the memory cells.

9. The memory device of claim 1 , wherein respective ones of the plurality of non-volatile memory cells comprise a second non-floating gate disposed over and insulated from the floating gate and a third non-floating gate disposed over and insulated from the source region, the memory device comprising:

a plurality of sixth lines, wherein respective ones of the plurality of sixth lines electrically connect together the second non-floating gates of odd row memory cells in one of the columns of the memory cells;

a plurality of seventh lines, wherein respective ones of the plurality of seventh lines electrically connect together the second non-floating gates of even row memory cells in one of the columns of the memory cells; and

a plurality of eighth lines, wherein respective ones of the plurality of eighth lines electrically connect together the third non-floating gates in one of the rows of the memory cells.

10. A memory device, comprising:

a plurality of memory cells arranged in rows and columns, wherein each column of the memory cells comprises:

a plurality of alternating source and drain regions formed in a semiconductor substrate, with two channel regions of the semiconductor substrate extending from each of the source regions to an adjacent two of the drain regions respectively, wherein the drain regions include first drain regions and second drain regions that alternate with each other;

a plurality of floating gates each disposed over and insulated from a first portion of one of the channel regions, and

a plurality of first non-floating gates each disposed over and insulated from a second portion of one of the channel regions;

wherein the source regions are arranged in rows and columns; and

a plurality of first lines each electrically connecting together the source regions in one of the rows of the source regions and physically isolated from the source regions in other rows of the source regions;

wherein for each one of the columns of memory cells, the memory device further comprising:

a second line electrically connecting together the first drain regions of the one column and physically isolated from the second drain regions of the one column,

a third line electrically connecting together the second drain regions of the one column and physically isolated from the first drain regions of the one column,

a fourth line electrically connecting together the first non-floating gates of odd row memory cells of the one column, and

a fifth line electrically connecting together the first non-floating gates of even row memory cells of the one column.

11. The memory device of claim 10 , wherein for each one of the columns of memory cells:

the second line is physically isolated from the drain regions in other columns of the memory cells; and

the third line is physically isolated from the drain regions in other columns of the memory cells.

12. The memory device of claim 10 , wherein each of the memory cells comprises a second non-floating gate disposed over and insulated from the floating gate, the memory device further comprising:

a plurality of sixth lines each electrically connecting together the second non-floating gates in one of the rows of the memory cells.

13. The memory device of claim 10 , wherein each of the memory cells comprises a second non-floating gate disposed over and insulated from the source region, the memory device further comprising:

a plurality of sixth lines each electrically connecting together the second non-floating gates in one of the columns of the memory cells.

14. The memory device of claim 10 , wherein for each one of the columns of the memory cells:

the fourth line is physically isolated from the first non-floating gates in other columns of the memory cells; and

the fifth line is physically isolated from the first non-floating gates in other columns of the memory cells.

15. The memory device of claim 10 , wherein each of the memory cells comprises a second non-floating gate disposed over and insulated from the floating gate and a third non-floating gate disposed over and insulated from the source region, the memory device further comprising:

a plurality of sixth lines each electrically connecting together the second non-floating gates in one of the rows of the memory cells; and

a plurality of seventh lines each electrically connecting together the third non-floating gates in one of the columns of the memory cells.

16. The memory device of claim 10 , wherein each of the memory cells comprises a second non-floating gate disposed over and insulated from the floating gate and a third non-floating gate disposed over and insulated from the source region, the memory device further comprising:

a plurality of sixth lines each electrically connecting together the second non-floating gates in one of the rows of the memory cells;

a plurality of seventh lines each electrically connecting together the third non-floating gates in one of the columns of the memory cells.

17. The memory device of claim 10 , wherein each of the memory cells comprises a second non-floating gate disposed over and insulated from the floating gate, the memory device further comprising:

a plurality of sixth lines each electrically connecting together the second non-floating gates of odd row memory cells in one of the columns of the memory cells; and

a plurality of seventh lines each electrically connecting together the second non-floating gates of even row memory cells in one of the columns of the memory cells.

18. The memory device of claim 10 , wherein each of the memory cells comprises a second non-floating gate disposed over and insulated from the source region, the memory device further comprising:

a plurality of sixth lines each electrically connecting together the second non-floating gates in one of the rows of the memory cells.

19. The memory device of claim 10 , wherein each of the memory cells comprises a second non-floating gate disposed over and insulated from the floating gate and a third non-floating gate disposed over and insulated from the source region, the memory device further comprising:

a plurality of sixth lines each electrically connecting together the second non-floating gates of odd row memory cells in one of the columns of the memory cells;

a plurality of seventh lines each electrically connecting together the second non-floating gates of even row memory cells in one of the columns of the memory cells; and

a plurality of eighth lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells.

20. The memory device of claim 10 , wherein each of the memory cells comprises a second non-floating gate disposed over and insulated from the floating gate and a third non-floating gate disposed over and insulated from the source region, the memory device further comprising:

a plurality of sixth lines each electrically connecting together the second non-floating gates of odd row memory cells in one of the columns of the memory cells;

a plurality of seventh lines each electrically connecting together the second non-floating gates of even row memory cells in one of the columns of the memory cells; and

a plurality of eighth lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2025
From: STRUKOV, DMITRI B.; GUO, XINJIE; BAYAT, FARNOOD MERRIKH; DO, NHAN; TRAN, HIEU VAN; TIWARI, VIPIN; REITEN, MARK
To: SILICON STORAGE TECHNOLOGY, INC.; THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Reel/Frame 070944/0738 →
Continuity (4)
Continuation 17580862 · Jan 21, 2022
Continuation 15594439 · May 12, 2017
Provisional Application 62337760 · May 17, 2016
Related Publication 20230259738A1 · Aug 17, 2023
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