Granted Patent B2

US 12,622,252 · App. 18/141,552 · Granted May 5, 2026

Inventors: Albert M. Chu (Nashua, NH); Junli Wang (Slingerlands, NY); Brent A. Anderson (Jericho, VT); Leon Sigal (Monsey, NY); David Wolpert (Poughkeepsie, NY); Ruilong Xie (Niskayuna, NY); Jay William Strane (Wappingers Falls, NY)

Assignee: International Business Machines Corporation

H10W20/20H10D30/014H10D30/43H10D30/6729H10D30/6735H10D30/6757H10D62/121H10D64/017H10D84/017H10D84/0186H10D84/038H10D84/85

Abstract

Claims (44)

1 . A semiconductor structure comprising:

a first transistor, wherein the first transistor comprises a first input source/drain region and a first output source/drain region;

a second transistor, wherein the second transistor comprises a second input source/drain region and a second output source/drain region;

a first source/drain contact commonly connected to the first input source/drain region and the second input source/drain region;

a second source/drain contact commonly connected to the first output source/drain region and the second output source/drain region;

a third source/drain contact connecting the first input source/drain region and the second input source/drain region to a first power rail; and

a fourth source/drain contact connecting the first output source/drain region and the second output source/drain region to second power rail;

wherein the first source/drain contact and the second source/drain contact are on a first side of the semiconductor structure; and

wherein the third source/drain contact and the fourth source/drain contact are on a second side of the semiconductor structure, opposite the first side.

2 . The semiconductor structure of claim 1 , wherein:

the first side of the semiconductor structure comprises a frontside of the semiconductor structure; and

the second side of the semiconductor structure comprises a backside of the semiconductor structure.

3 . The semiconductor structure of claim 2 , wherein at least one edge of the first source/drain contact is self-aligned with at least one edge of the first input source/drain region.

4 . The semiconductor structure of claim 3 , wherein at least one edge of the second source/drain contact is self-aligned with at least one edge of the second output source/drain region.

5 . The semiconductor structure of claim 1 , further comprising at least one gate structure common to the first transistor and the second transistor.

6 . The semiconductor structure of claim 1 , wherein the first transistor and the second transistor have a same doping type.

7 . The semiconductor structure of claim 6 , further comprising a third transistor adjacent the second transistor, wherein the third transistor has a different doping type than that of the first transistor and the second transistor.

8 . The semiconductor structure of claim 1 , wherein the first transistor and the second transistor are nanosheet transistors.

9 . A semiconductor structure comprising:

a plurality of input source/drain regions connected to a first wire through a first contact; and

a plurality of output source/drain regions connected to a second wire through a second contact;

wherein the first wire and the second wire are on a same side of the semiconductor structure; and

wherein the plurality of input source/drain regions and the plurality of output source/drain regions correspond to a merged transistor, wherein the merged transistor comprises a first transistor and a second transistor.

10 . The semiconductor structure of claim 9 , wherein the same side of the semiconductor structure comprises a backside of the first transistor and of the second transistor.

11 . The semiconductor structure of claim 9 , further comprising a third transistor adjacent the merged transistor and at least one gate structure common to the merged transistor and the third transistor, wherein:

the first transistor and the second transistor have a same doping type; and

the third transistor has a different doping type than that of the first transistor and the second transistor.

12 . The semiconductor structure of claim 9 , wherein the first transistor and the second transistor are nanosheet transistors.

13 . The semiconductor structure of claim 9 , wherein:

the first wire comprises a first power rail; and

the second wire comprises a second power rail.

14 . A semiconductor structure comprising:

a plurality of transistors comprising a first transistor, a second transistor adjacent the first transistor and a third transistor adjacent the second transistor, wherein the first transistor and the second transistor have a same doping type, and the third transistor has a different doping type than that of the first transistor and the second transistor;

at least one gate structure common to the first transistor, the second transistor and the third transistor;

a first input source/drain region and a first output source/drain region corresponding to the first transistor; and

a second input source/drain region and a second output source/drain region corresponding to the second transistor;

wherein the first input source/drain region and the second input source/drain region are connected to a first source/drain contact; and

wherein the first output source/drain region and the second output source/drain region are connected to a second source/drain contact.

15 . The semiconductor structure of claim 14 , wherein:

at least one edge of the first source/drain contact is self-aligned with at least one edge of the first input source/drain region; and

at least one edge of the second source/drain contact is self-aligned with at least one edge of the second output source/drain region.

16 . The semiconductor structure of claim 14 , wherein the first source/drain contact and the second source/drain contact are disposed on a backside of the plurality of transistors and are respectively connected to a first wire and a second wire disposed on the backside of the plurality of transistors.

17 . The semiconductor structure of claim 16 , wherein the first wire contacts the first source/drain contact, and the second wire contacts the second source/drain contact.

18 . The semiconductor structure of claim 14 , wherein the plurality of transistors comprises a plurality of nanosheet transistors.

Assignments (1)

Continuity (1)

References Cited (16)