IP Library › Granted Patent US 12,095,474
Granted Patent B1
US 12,095,474 · App. 18/146,026 · Granted Sep 17, 2024

Using multiple error correction code decoders to store extra data in a memory system

Inventors: Jun Zhu (San Jose, CA); Biswanath Tayenjam (Bangalore, IN)
Assignee: Synopsys, Inc.
H03M13/03H03M13/37
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Quick Facts
Patent No.
US 12,095,474
App. No.
18/146,026
Granted
Sep 17, 2024
Kind
B1
Abstract

Disclosed is a configuration to store metadata using an error correction code (ECC). The configuration receives at an ECC encoder of a memory controller, write data and an N-bit metadata, N comprising an integer greater than 0. The configuration generates a meta symbol using the N-bit metadata and creates an enhanced write data, the enhanced write data comprising the write data and the meta symbol generated by the N-bit metadata. The configuration encodes the enhanced write data and meta symbol to generate a parity. It deletes the meta symbol to generate an output, the output comprising an enhanced codeword and writes the enhanced codeword to a memory.

Claims (45)

1. A method for storing metadata using an error correction code (ECC), the method comprising:

receiving at an ECC encoder of a memory controller, write data and an N-bit metadata, N comprising an integer greater than 0;

generating a meta symbol using the N-bit metadata;

creating enhanced write data by combining the write data and the meta symbol;

generating a parity based on the enhanced write data;

generating a codeword by combining the enhanced write data and the parity;

generating an enhanced codeword by deleting the meta symbol from the codeword; and

writing the enhanced codeword to a memory.

2. The method of claim 1 , wherein N-bit metadata is one-bit metadata and the enhanced codeword comprises the write data and the parity based on the meta symbol and write data and wherein the memory transmits the enhanced codeword to a first decoder and a second decoder.

3. The method of claim 2 , wherein the first decoder adds a first meta symbol to the enhanced codeword to generate a first augmented codeword and the second decoder adds a second meta symbol to the enhanced codeword to generate a second augmented codeword.

4. The method of claim 3 , wherein the first decoder decodes the first augmented codeword and corrects errors for a first decoded data and the second decoder decodes the second augmented codeword and corrects errors for a second decoded data.

5. The method of claim 4 , wherein if the first decoded data has one error and the second decoded data has zero error, extracting from the second meta symbol the one-bit metadata information associated with write data.

6. The method of claim 4 , wherein if the first decoded data has zero error and the second decoded data has one error, extracting from the first meta symbol the one-bit metadata information-associated with write data.

7. The method of claim 4 , wherein if the first decoded data has two errors and the second decoded data has one error, extracting from the second meta symbol the one-bit metadata information associated with write data.

8. The method of claim 4 , wherein if the first decoded data has one error and the second decoded data has two errors, extracting from the first meta symbol the one-bit metadata information associated with write data.

9. The method of claim 4 , wherein if the first decoded data has three or more errors and the second decoded data has two errors, extracting from the second meta symbol the one-bit metadata information associated with write data.

10. The method of claim 4 , wherein if the first decoded data has two errors and the second decoded data has three or more errors, extracting from the first meta symbol the one-bit metadata information associated with write data.

11. A non-transitory computer-readable storage medium comprising stored instructions for storing metadata using an error correction code (ECC), the instructions when executed by least one processor causes at least one processor to:

receive at an ECC encoder of a memory controller, write data and an N-bit metadata, N comprising an integer greater than 0;

generate a meta symbol using the N-bit metadata;

create enhanced write data by combining the write data and the meta symbol;

generate a parity based on the enhanced write data;

generate a codeword by combining the enhanced write data and the parity;

generate an enhanced codeword by deleting the meta symbol from codeword; and

write the enhanced codeword to a memory.

12. The non-transitory computer-readable storage medium of claim 11 , wherein N-bit metadata is one-bit metadata and the enhanced codeword comprises the write data and the parity based on the meta symbol and write data.

13. The non-transitory computer-readable storage medium of claim 12 , further comprising stored instructions that when executed causes the at least one processor to:

receive from the memory the enhanced codeword at a first decoder and a second decoder;

instruct the first decoder to add a first meta symbol to the enhanced codeword to generate a first augmented codeword; and

instruct the second decoder to add a second meta symbol to the enhanced codeword to generate a second augmented codeword.

14. The non-transitory computer-readable storage medium of claim 13 , further comprising stored instructions that when executed causes the at least one processor to:

instruct the first decoder to decode the first augmented codeword and correct errors for a first decoded data; and

instruct the second decoder to decode the second augmented codeword and correct errors for a second decoded data.

15. The non-transitory computer-readable storage medium of claim 14 , further comprising stored instructions that when executed causes the at least one processor to:

extract from the second meta symbol the one-bit metadata associated with write data if the first decoded data has one error and the second decoded data has zero error.

16. The non-transitory computer-readable storage medium of claim 14 , further comprising stored instructions that when executed causes the at least one processor to:

extract from the first meta symbol the one-bit metadata associated with write data wherein if the first decoded data has zero error and the second decoded data has one error.

17. The non-transitory computer-readable storage medium of claim 14 , further comprising stored instructions that when executed causes the at least one processor to:

extract from the second meta symbol the one-bit metadata associated with write data wherein if the first decoded data has two errors and the second decoded data has one error.

18. The non-transitory computer-readable storage medium of claim 14 , further comprising stored instructions that when executed causes the at least one processor to:

extract from the first meta symbol the one-bit metadata associated with write data wherein if the first decoded data has one error and the second decoded data has two errors.

19. The non-transitory computer-readable storage medium of claim 14 , further comprising stored instructions that when executed causes the at least one processor to:

extract from the second meta symbol the one-bit metadata associated with write data wherein if the first decoded data has three or more errors and the second decoded data has two errors.

20. The non-transitory computer-readable storage medium of claim 14 , further comprising stored instructions that when executed causes the at least one processor to:

extract from the first meta symbol the one-bit metadata associated with write data wherein if the first decoded data has two errors and the second decoded data has three or more errors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2022
From: ZHU, JUN; TAYENJAM, BISWANATH
To: SYNOPSYS, INC.
Reel/Frame 062198/0634 →
Continuity (1)
Provisional Application 63306464 · Feb 3, 2022
Cited By (12)
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