Universal pointers for data exchange in a computer system having independent processors
A system, method and apparatus to facilitate data exchange via pointers. For example, in a computing system having a first processor and a second processor that is separate and independent from the first processor, the first processor can run a program configured to use a pointer identifying a virtual memory address having an ID of an object and an offset within the object. The first processor can use the virtual memory address to store data at a memory location in the computing system and/or identify a routine at the memory location for execution by the second processor. After the pointer is communicated from the first processor to the second processor, the second processor can access the same memory location identified by the virtual memory address. The second processor may operate on the data stored at the memory location or load the routine from the memory location for execution.
1. A device, comprising:
a first processor configured to:
receive, from a second processor, a pointer identifying a virtual memory address in a computing system, the pointer comprising at least an offset representing a memory location offset within an object, an object type associated with the object, and an object identifier having a first number of bits, wherein the object type has a value that identifies the object associated with the object identifier;
apply a hash to the object identifier, a portion of the offset representing the memory location offset within the object, and the object type provided as a portion of the pointer to generate an index from the pointer, wherein the index has a second number of bits that is fewer than the first number of bits;
determine, based on the index, an entry in an address translation table that identifies a base of a physical address corresponding to the virtual memory address;
access a physical memory location represented by the virtual memory address using the entry determined based on the index from the address translation table; and
combine the base identified in the entry with a remaining portion of the offset to generate the physical address.
2. The device of claim 1 , wherein the second processor is separate and independent from the first processor.
3. The device of claim 1 , wherein the first processor and the second processor have different instruction set architecture (ISA).
4. The device of claim 1 , wherein the first processor is running a first operating system and the second processor is running a second operating system different from the first operating system.
5. The device of claim 4 , wherein:
the first operating system is Linux and the second operating system is Windows; or
the first operating system is Windows and the second operating system is Linux.
6. The device of claim 1 , wherein the pointer is communicated from the second processor to the first processor via a computer network.
7. The device of claim 1 , wherein the physical memory location is located in a storage device directly accessible to the first processor, further wherein the storage device is only accessible to the second processor via communication with the first processor.
8. The device of claim 1 , wherein the first processor is further configured to:
load an instruction from the physical memory location into the first processor; and
execute the instruction in the first processor.
9. The device of claim 1 , wherein the first processor is further configured to:
load an operand from the physical memory location into the first processor in response to the virtual memory address being in a register in the first processor; and
execute an instruction on the operand in the first processor.
10. The device of claim 1 , wherein in determination, based on the hash, of the entry in the address translation table the first processor is configured to:
send, to an object name server, the index; and
receive, from the object name server in response to the index, the entry in the address translation table.
11. A system, comprising:
a first processor;
a second processor in communication with the first processor;
memory directly accessible to the first processor, wherein the memory is only accessible to the second processor via communication with the first processor,
wherein the first processor is configured to:
receive, from the second processor, a pointer identifying a virtual memory address in the system, the pointer comprising at least an object identifier having a first number of bits, an offset representing a memory location offset within an object, and an object type having a value identifying the object associated with the object identifier;
apply a hash to a portion of the pointer comprising the object identifier, a portion of the offset representing the memory location offset within the object, and the object type to generate an index from the pointer, wherein the index has a second number of bits that is fewer than the first number of bits;
determine, based on the index, an entry in an address translation table that identifies a base of a physical address corresponding to the virtual memory address;
access, in the memory, a physical memory location represented by the virtual memory address using the entry determined based on the index from the address translation table; and
combine the base identified in the entry with a remaining portion of the offset to generate the physical address.
12. The system of claim 11 , wherein in determination, based on the hash, of the entry in the address translation table the first processor is configured to:
send, to an object name server, the index; and
receive, from the object name server in response to the index, the entry in the address translation table.
13. The system of claim 12 , wherein the object name server is configured to:
receive, from the first processor, the index;
look up a physical address in the address translation table using the index, wherein the address translation table is stored in the object name server; and
send, to the first processor, the entry in the address translation table.
14. The system of claim 11 , wherein in determination, based on the hash, of the entry in the address translation table the first processor is configured to make a determination that the index references multiple entries in the address translation table.
15. The system of claim 14 , wherein, upon making the determination that the index references multiple entries in the address translation table, the determination of the entry in the address translation table further comprises using a collision chain to identify a unique address associated with the virtual memory address.
16. The system of claim 11 , wherein the second processor is separate and independent from the first processor.
17. The system of claim 11 , wherein the first processor and the second processor have different instruction set architecture (ISA).
18. The system of claim 11 , wherein the first processor is running a first operating system and the second processor is running a second operating system different from the first operating system.
19. A device, comprising:
a first processor; and
first memory connected to the first processor, wherein an address translation table is stored on the memory, wherein the first processor is configured to:
receive, from a second processor, an index comprising a hash of a portion of a pointer, wherein the pointer identifies a virtual memory address and the portion of the pointer comprises an object identifier, an object type having a value that identifies an object associated with the object identifier, and an offset representing a memory location offset within an object;
look up an entry in the address translation table using the index, wherein the entry identifies a base of a physical address corresponding to the virtual memory address;
access, using the entry from the address translation table, the physical memory location; and
combine the base identified in the entry with a remaining portion of the offset to generate the physical address.
20. The device of claim 19 , wherein the pointer comprises at least an object identifier having a first number of bits, and further wherein the index has a second number of bits that is fewer than the first number of bits.