Chip packaging method and chip packaging structure
The present disclosure provides a chip packaging method and a chip packaging structure. The chip packaging method includes: providing an encapsulated grain and a packaging substrate, the encapsulated grain including a first hybrid bonding structure; wherein the packaging substrate includes a front side and a back side opposite to each other; a second hybrid bonding structure is formed on the front side of the packaging substrate and a connection pin is formed on the back side of the packing substrate; the second hybrid bonding structure and the connection pin are electrically connected through a third connecting metal column penetrating the packaging substrate; and bonding together the first hybrid bonding structure of the encapsulated grain and the second hybrid bonding structure of the packaging substrate by medium-to-medium and metal-to-metal aligned bonding such that the encapsulated grain is bonded to the packaging substrate.
1 . A chip packaging method, comprising:
providing an encapsulated grain and a packaging substrate, the encapsulated grain comprising a plurality of first hybrid bonding structures, a plurality of third hybrid bonding structures arranged inside the encapsulated grain, and at least one chip; wherein the packaging substrate is a ceramic substrate and comprises a front side and a back side opposite to each other; a plurality of second hybrid bonding structures are formed on the front side of the packaging substrate and a plurality of connection pins are formed on the back side of the packing substrate; the plurality of second hybrid bonding structures are electrically connected to the plurality of connection pins through a plurality of metal posts penetrating the packaging substrate; and
bonding together the plurality of first hybrid bonding structures of the encapsulated grain with the plurality of second hybrid bonding structures of the packaging substrate by medium-to-medium and metal-to-metal aligned bonding such that the encapsulated grain is bonded to the packaging substrate;
the encapsulated grain further comprises a wafer; the at least one chip is bonded to the wafer, and a side of the wafer away from the at least one chip is formed with the plurality of first hybrid bonding structures; the plurality of third hybrid bonding structures are formed on a side of the wafer bonded to the at least one chip;
the wafer comprises a first semiconductor substrate, and a first dielectric layer and a second dielectric layer laminated on opposite sides of the first semiconductor substrate; the plurality of first hybrid bonding structures are formed in the second dielectric layer; the plurality of third hybrid bonding structures are formed on a side surface of the first dielectric layer away from the first semiconductor substrate;
the plurality of third hybrid bonding structures are bonded to the at least one chip; and a pitch of any adjacent two of the plurality of first hybrid bonding structures bonding the wafer to the packaging substrate is greater than a pitch of any adjacent two of the plurality of third hybrid bonding structures bonding the wafer to the at least one chip.
2 . The chip packaging method according to claim 1 , wherein each of the plurality of connection pins comprises a metal bump and/or a metal solder ball.
3 . The chip packaging method according to claim 1 , wherein each of the at least one chip corresponds to two of the plurality of first hybrid bonding structures and two of the plurality of third hybrid bonding structures, and an orthographic projection of each of the two first hybrid bonding structures and the two third hybrid bonding structures on the packaging substrate is within an orthographic projection of the chip on the packaging substrate.
4 . The chip packaging method according to claim 1 , further comprising:
performing an annealing process to cause the plurality of first hybrid bonding structures and the plurality of second hybrid bonding structures to expand and bond together; wherein the annealing process is at a temperature of 550° C. to 650° C.
5 . A chip packaging structure, comprising:
an encapsulated grain, comprising a plurality of first hybrid bonding structures, a plurality of third hybrid bonding structures arranged inside the encapsulated grain, and at least one chip; and
a packaging substrate, being a ceramic substrate and comprising a front side and a back side opposite to each other; a plurality of second hybrid bonding structures are formed on the front side of the packaging substrate and a plurality of connection pins are formed on the back side of the packing substrate; the plurality of second hybrid bonding structures are electrically connected to the plurality of connection pins through a plurality of metal posts penetrating the packaging substrate;
wherein each of the plurality of first hybrid bonding structures of the encapsulated grain is bonded to a respective one of the plurality of second hybrid bonding structures of the packaging substrate by medium-to-medium and metal-to-metal aligned bonding such that the encapsulated grain is bonded to the packaging substrate;
the encapsulated grain further comprises a wafer; the at least one chip is bonded to the wafer, and a side of the wafer away from the at least one chip is formed with the plurality of first hybrid bonding structures; the plurality of third hybrid bonding structures are formed on a side of the wafer bonded to the at least one chip;
the wafer comprises a first semiconductor substrate, and a first dielectric layer and a second dielectric layer laminated on opposite sides of the first semiconductor substrate; the plurality of first hybrid bonding structures are formed in the second dielectric layer; the plurality of third hybrid bonding structures are formed on a side surface of the first dielectric layer away from the first semiconductor substrate;
the plurality of third hybrid bonding structures are bonded to the at least one chip; and a pitch of any adjacent two of the plurality of first hybrid bonding structures bonding the wafer to the packaging substrate is greater than a pitch of any adjacent two of the plurality of third hybrid bonding structures bonding the wafer to the at least one chip.
6 . The chip packaging structure according to claim 5 , wherein each of the plurality of connection pins comprises a metal bump and/or a metal solder ball.
7 . The chip packaging structure according to claim 5 , wherein each of the at least one chip corresponds to two of the plurality of first hybrid bonding structures and two of the plurality of third hybrid bonding structures, and an orthographic projection of each of the two first hybrid bonding structures and the two third hybrid bonding structures on the packaging substrate is within an orthographic projection of the chip on the packaging substrate.
8 . The chip packaging structure according to claim 5 , wherein the wafer comprises a first semiconductor substrate, and a first dielectric layer and a second dielectric layer laminated on opposite sides of the first semiconductor substrate; a side surface of the second dielectric layer away from the first semiconductor substrate is taken as a pin surface.
9 . The chip packaging structure according to claim 8 , wherein at least one electronic device and at least one connecting metal column are formed in the first semiconductor substrate, and each of the at least one connecting metal column extends to a side surface of the first semiconductor substrate away from the first dielectric layer; the first hybrid bonding structure is formed in the second dielectric layer, electrically connected to the connecting metal column, and exposed from the pin surface.
10 . The chip packaging structure according to claim 9 , wherein at least one first interconnection structure is formed in the first dielectric layer, and each first interconnection structure is electrically connected to each connecting metal column in one-to-one correspondence; the third hybrid bonding structure comprises at least one third hybrid bonding structure, and each of the at least one third hybrid bonding structure is formed on a side surface of the first dielectric layer away from the first semiconductor substrate and is electrically connected to each first interconnection structure in one-to-one correspondence.
11 . The chip packaging structure according to claim 10 , wherein each chip comprises a second semiconductor substrate and a third dielectric layer; at least one electronic device is formed in the second semiconductor substrate, the third dielectric layer is laminated on the second semiconductor substrate and is attached to the first dielectric layer, and the third dielectric layer is formed with a second interconnection structure and a plurality of fourth hybrid bonding structures electrically connected to the second interconnection structure; the plurality of fourth hybrid bonding structures are formed on a side surface of the third dielectric layer away from the second semiconductor substrate; the plurality of fourth hybrid bonding structures are bonded to the plurality of third hybrid bonding structures for aligning and bonding the first dielectric layer with the third dielectric layer, and aligning and bonding the plurality of third hybrid bonding structures with the plurality of fourth hybrid bonding structures, to enable the chip to be bonded to the wafer.
12 . The chip packaging structure according to claim 5 , wherein the encapsulated grain further comprises an encapsulated layer, covering the at least one chip and a gap between adjacent two of the at least one chip.
13 . The chip packaging structure according to claim 5 , wherein the packaging substrate further comprises a third substrate and a fourth dielectric layer that are laminated; the third substrate comprises a first side and a second side opposite to each other; the second hybrid bonding structure is disposed on the first side of the third substrate, the connection pin is formed on the second side of the third substrate, and the metal post runs through the first side and second side of the third substrate.
14 . The chip packaging structure according to claim 13 , wherein the fourth dielectric layer is laminated to the first side of the third substrate and a side of the fourth dielectric layer away from the third substrate is taken as a substrate surface; the first hybrid bonding structure is arranged in the fourth dielectric layer, and the first hybrid bonding structure is connected to the second hybrid bonding structure and exposed from the substrate surface of the fourth dielectric layer.
15 . The chip packaging structure according to claim 13 , wherein the packaging substrate further comprises a fifth dielectric layer laminated on the second side of the third substrate; a metal connection block is formed in the fifth dielectric layer, arranged facing the metal post, and electrically connected to the metal post.
16 . The chip packaging structure according to claim 15 , wherein the connection pin is connected to a side surface of the metal connection block away from the metal post, to be indirectly electrically connected to the metal post through the metal connection block.
17 . The chip packaging structure according to claim 5 , further comprising a printed circuit board; wherein the connecting pin of the packaging substrate is bonded to a metal bump and/or a metal solder ball of the printed circuit board.