Multi-chip package structures with discrete redistribution layers
Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.
1. A package structure, comprising:
a package substrate, wherein the package substrate comprises a recessed cavity formed in an upper surface of the package substrate;
an interconnect bridge device, wherein the interconnect bridge device is disposed within the recessed cavity;
a first chip package comprising a first redistribution layer structure and a first integrated circuit chip connected to the first redistribution layer structure, wherein the first redistribution layer structure is flip-chip connected to the interconnect bridge device and to the upper surface of the package substrate using a first array of solder bump connections between the first redistribution layer structure and the upper surface of the package substrate, and a second array of solder bump connections between the first redistribution layer structure and the interconnect bridge device; and
a second chip package comprising a second redistribution layer structure and a second integrated circuit chip connected to the second redistribution layer structure, wherein the second redistribution layer structure is flip-chip connected to the interconnect bridge device and to the upper surface of the package substrate using a third array of solder bump connections between the second redistribution layer structure and the upper surface of the package substrate, and a fourth array of solder bump connections between the second redistribution layer structure and the interconnect bridge device;
wherein the first and second redistribution layer structures are separate from each other;
wherein the interconnect bridge device comprises wiring to provide package-to-package connections between the first and second chip packages.
2. The package structure of claim 1 , wherein the interconnect bridge device further comprises wiring to provide connections between the package substrate and at least one of the first and second chip packages.
3. The package structure of claim 1 , wherein the first and second redistribution layer structures comprise fan-out redistribution layer structures.
4. The package structure of claim 1 , wherein:
the first redistribution layer structure is formed directly on an active surface of the first integrated circuit chip; and
the second redistribution layer structure is formed directly on an active surface of the second integrated circuit chip.
5. The package structure of claim 1 , wherein the first, second, third, and fourth arrays of solder bump connections each comprise solder bumps disposed at a bump pitch of 55 microns or less.
6. The package structure of claim 1 , wherein:
the first and third arrays of solder bump connections each comprise solder bumps disposed at a bump pitch of greater than 55 microns; and
the second and fourth arrays of solder bump connections each comprise solder bumps disposed at a bump pitch of 55 microns or less.
7. The package structure of claim 1 , wherein the interconnect bridge device comprises a build-up of multiple layers of inorganic dielectric material and patterned metallization to provide interlayer vias and lateral traces to form the wiring of the interconnect bridge device.
8. The package structure of claim 1 , wherein the first integrated circuit chip comprises a memory die and wherein the second integrated circuit chip comprises a processor die.
9. The package structure of claim 1 , wherein the package substrate comprises one of a ceramic substrate and an organic laminate build-up substrate.
10. The package structure of claim 1 , wherein the first integrated circuit chip is connected to the first redistribution layer structure with an array of solder bumps.
11. The package structure of claim 1 , wherein the first redistribution layer structure is disposed on an active surface of the first integrated circuit chip.
12. A package structure, comprising:
a package substrate comprising an upper surface;
an interconnect bridge device mounted to the upper surface of the package substrate;
a first chip package comprising a first redistribution layer structure and a first integrated circuit chip connected to the first redistribution layer structure, wherein the first redistribution layer structure is flip-chip connected to the interconnect bridge device and to the upper surface of the package substrate using a first array of solder bump connections between the first redistribution layer structure and the upper surface of the package substrate, and a second array of solder bump connections between the first redistribution layer structure and the interconnect bridge device; and
a second chip package comprising a second redistribution layer structure and a second integrated circuit chip connected to the second redistribution layer structure, wherein the second redistribution layer structure is flip-chip connected to the interconnect bridge device and to the upper surface of the package substrate using a third array of solder bump connections between the second redistribution layer structure and the upper surface of the package substrate, and a fourth array of solder bump connections between the second redistribution layer structure and the interconnect bridge device;
wherein the first and second redistribution layer structures are separate from each other;
wherein the interconnect bridge device comprises wiring to provide package-to-package connections between the first and second chip packages;
wherein the package structure comprises standoff connection structures disposed between the upper surface of the package substrate and the first and second chip packages, wherein the standoff connection structures are configured to offset a height of the interconnection bridge device mounted to the upper surface of the package substrate.
13. The package structure of claim 12 , wherein the standoff structures comprise one of (i) copper pillar structures and (ii) solder-coated copper balls that are formed on contact pads on one of (i) upper surface of the package substrate, (ii) bottom sides of the first and second chip packages and (iii) both the upper surface of the package substrate and the bottom sides of the first and second chip packages.
14. The package structure of claim 12 , wherein the interconnect bridge device further comprises wiring to provide connections between the package substrate and at least one of the first and second chip packages.
15. The package structure of claim 12 , wherein the first and second redistribution layer structures comprise fan-out redistribution layer structures.
16. The package structure of claim 12 , wherein:
the first and third arrays of solder bump connections each comprise solder bumps disposed at a bump pitch of greater than 55 microns; and
the second and fourth arrays of solder bump connections each comprise solder bumps disposed at a bump pitch of 55 microns or less.
17. The package structure of claim 12 , wherein the interconnect bridge device comprises a build-up of multiple layers of inorganic dielectric material and patterned metallization to provide interlayer vias and lateral traces to form the wiring of the interconnect bridge device.
18. The package structure of claim 12 , wherein the first integrated circuit chip comprises a memory die and wherein the second integrated circuit chip comprises a processor die.
19. The package structure of claim 12 , wherein the first integrated circuit chip is connected to the first redistribution layer structure with an array of solder bumps.
20. The package structure of claim 12 , wherein the first redistribution layer structure is disposed formed directly on an active surface of the first integrated circuit chip.