Memory chiplet with efficient mapping of memory-centric interface to die-to-die (D2D) unit interface modules
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes a D2D interface of a first type for coupling to a host IC chip via multiple lanes. The D2D interface includes multiple unit interface modules, each of the multiple unit interface modules corresponding to a first set of signal path resources of a lowest granularity provided by the multiple lanes. A memory port includes a memory physical interface of a first memory type for accessing memory storage of the first memory type. The memory physical interface of the first memory type includes a second set of signal path resources corresponding to multiple memory channels of the first memory type. Mapping circuitry maps the second set of signal path resources to the first set of signal path resources in a manner that utilizes all of the first signal path resources for an integer number of the multiple unit interface modules.
1. A chiplet-based multi-chip module (MCM) to couple to a base substrate, comprising:
a package substrate that is separate from the base substrate;
a host integrated circuit (IC) chiplet coupled to the package substrate and comprising:
at least one processing element;
a first die-to-die (D2D) interface of a first type to transfer memory information from the at least one processing element via a communications fabric;
a memory chiplet comprising:
a second D2D interface of the first type coupled to the first D2D interface via multiple lanes, the second D2D interface organized into multiple unit interface modules, each of the multiple unit interface modules corresponding to a first set of signal path resources of a lowest granularity provided by the multiple lanes;
a memory port comprising a memory physical interface of a first memory type to access memory storage of the first memory type, the memory physical interface of the first memory type comprising a second set of signal path resources corresponding to multiple memory channels of a first memory type; and
mapping circuitry to map the second set of signal path resources to the first set of signal path resources in a manner that utilizes all of the first set of signal path resources for an integer number of the multiple unit interface modules.
2. The chiplet-based MCM of claim 1 , wherein:
each module corresponds to signal path resources for more than one memory channel of the first memory type.
3. The chiplet-based MCM of claim 1 , wherein:
the first set of signal path resources comprises unidirectional data paths; and
the second set of signal path resources comprises bidirectional data paths.
4. The chiplet-based MCM of claim 3 , wherein:
the first D2D interface of the first type comprises a Universal Chiplet Interface Express (UCIe) interface; and
the memory physical interface of the first memory type comprises a High-Bandwidth Memory (HBM) physical interface.
5. The chiplet-based MCM of claim 1 , wherein:
the first set of signal path resources comprises bidirectional data paths; and
the second set of signal path resources comprises bidirectional data paths.
6. The chiplet-based MCM of claim 5 , wherein:
the first D2D interface of the first type comprises a Universal Memory Interface (UMI) interface; and
the memory physical interface of the first memory type comprises a High-Bandwidth Memory (HBM) physical interface.
7. The chiplet-based MCM of claim 1 , wherein the mapping circuitry further comprises:
a selectable first mapping circuit for a first mode of operation; and
a selectable second mapping circuit for a second mode of operation.
8. The chiplet-based MCM of claim 1 , wherein:
the first memory type comprises High-Bandwidth Memory (HBM).
9. The chiplet-based MCM of claim 1 , wherein:
the second D2D interface, the memory port and the mapping circuitry of the memory chiplet are formed in a base die; and
the memory storage comprises at least one memory die of the first memory type stacked on the base die.
10. The chiplet-based MCM of claim 1 , wherein the memory chiplet further comprises:
a memory controller of the first memory type.
11. A memory chiplet, comprising:
a D2D interface of a first type to couple to a host IC chip via multiple lanes, the D2D interface of the first type comprising multiple unit interface modules, each of the multiple unit interface modules corresponding to a first set of signal path resources of a lowest granularity provided by the multiple lanes;
a memory port comprising a memory physical interface of a first memory type to access memory storage of the first memory type, the memory physical interface of the first memory type comprising a second set of signal path resources corresponding to multiple memory channels of the first memory type; and
mapping circuitry to map the second set of signal path resources to the first set of signal path resources for an integer number of the multiple unit interface modules.
12. The memory chiplet of claim 11 , wherein:
each module corresponds to signal path resources for more than one memory channel of the first memory type.
13. The memory chiplet of claim 11 , wherein:
the first set of signal path resources comprises unidirectional data paths; and
the second set of signal path resources comprises bidirectional data paths.
14. The memory chiplet of claim 13 , wherein:
the D2D interface of the first type comprises a Universal Chiplet Interface Express (UCIe) interface; and
the memory physical interface of the first memory type comprises a High-Bandwidth Memory (HBM) physical interface.
15. The memory chiplet of claim 11 , wherein:
the first set of signal path resources comprises bidirectional data paths; and
the second set of signal path resources comprises bidirectional data paths.
16. The memory chiplet of claim 15 , wherein:
the D2D interface of the first type comprises a Universal Memory Interface (UMI) interface; and
the memory physical interface of the first memory type comprises a High-Bandwidth Memory (HBM) physical interface.
17. The memory chiplet of claim 11 , wherein the mapping circuitry further comprises:
a selectable first mapping circuit for a first mode of operation; and
a selectable second mapping circuit for a second mode of operation.
18. The memory chiplet of claim 11 , wherein:
the first memory type comprises High-Bandwidth Memory (HBM).
19. The memory chiplet of claim 11 , wherein:
the D2D interface of the first type, the memory port and the mapping circuitry of the memory chiplet are formed in a base die; and
the memory storage comprises at least one memory die of the first memory type stacked on the base die.
20. The memory chiplet of claim 11 , wherein the memory chiplet further comprises:
a memory controller of the first memory type.