Multi-chip module (MCM) with interface adapter circuitry
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and a first integrated circuit (IC) chip disposed on the package substrate. The first IC chip includes first core circuitry, and first interface circuitry for communicating with the first core circuitry. A second IC chip is disposed on the package substrate and includes second core circuitry and second interface circuitry for communicating with the second core circuitry. The second interface circuitry exhibits a non-matching interface with respect to the first interface circuitry. Interface adapter circuitry couples to the first interface circuitry and the second interface circuitry to establish a common physical interface (PHY) for communicating between the first core circuitry and the second core circuitry.
1. A multi-chip module (MCM), comprising:
a package substrate;
a first integrated circuit (IC) chip disposed on the package substrate, the first IC chip including
first core circuitry, and
first interface circuitry for communicating with the first core circuitry;
a second IC chip disposed on the package substrate, the second IC chip including
second core circuitry, and
second interface circuitry for communicating with the second core circuitry, the second interface circuitry exhibiting a non-matching interface with respect to the first interface circuitry; and
interface adapter circuitry including an interface adapter IC chip, the interface adapter IC chip coupled to the first interface circuitry and the second interface circuitry to establish a common physical interface (PHY) for communicating between the first core circuitry and the second core circuitry.
2. The MCM of claim 1 , wherein the interface adapter chip includes:
a first interface that matches the first interface circuitry of the first IC chip;
a first ultra-short-reach (USR) interface; and
a first conversion circuit coupled between the first interface and the first USR interface to convert a first set of signal paths that is compatible for connecting to the first interface to a second set of signal paths that is compatible for connecting to the first USR interface; and
wherein the MCM further includes at least one signaling link routed on the package substrate and configured to couple the first USR interface of the interface adapter IC chip to the second IC chip.
3. The MCM of claim 2 , wherein:
the second interface circuitry for communicating with the second core circuitry comprises a second USR interface for communicating with the first USR interface of the interface adapter IC chip over the at least one signaling link.
4. The MCM of claim 2 , wherein the interface adapter circuitry further comprises:
a second interface adapter IC chip, the second interface adapter IC chip including
a second interface that matches the second interface circuitry of the second IC chip;
a second ultra-short-reach (USR) interface; and
a second conversion circuit coupled between the second interface and the second USR interface to convert a third set of signal paths that is compatible for connecting to the second interface to a fourth set of signal paths that is compatible for connecting to the second USR interface, the second USR interface coupled to the at least one signaling link for communicating with the first USR interface of the interface adapter IC chip.
5. The MCM of claim 2 , wherein:
the first IC chip is stacked vertically above the interface adapter IC chip.
6. The MCM of claim 2 , wherein:
the interface adapter IC chip is encapsulated in a mold material to form a stack base; and
the first IC chip comprises a stack of IC chips mounted vertically on the stack base.
7. The MCM of claim 6 , wherein the stack base further includes:
a dummy chip encapsulated in the mold material and positioned horizontally with respect to the interface adapter IC chip.
8. The MCM of claim 2 , wherein the first IC chip further comprises:
a secondary substrate for mounting to the package substrate;
wherein the interface adapter IC chip is disposed on the secondary substrate; and
wherein the first IC chip is disposed on the secondary substrate and positioned in a horizontal relationship with the interface adapter IC chip.
9. The MCM of claim 2 , wherein the first IC chip further comprises:
a secondary substrate for mounting to the package substrate;
wherein the interface adapter IC chip is disposed on the secondary substrate; and
wherein the first IC chip is disposed on the secondary substrate and positioned in a vertical relationship with the interface adapter IC chip.
10. A multi-chip module (MCM), comprising:
a non-silicon substrate;
a first integrated circuit (IC) chip assembly disposed on the non-silicon substrate, the first IC chip assembly including
multiple IC chips positioned in a vertical relationship to form a chip stack;
first interface circuitry for communicating with the multiple IC chips; and
an interface adapter chip stacked with the chip stack;
a second IC chip assembly disposed on the non-silicon substrate, the second IC chip assembly having second interface circuitry, the second interface circuitry exhibiting a non-matching interface with respect to the first interface circuitry; and
wherein the interface adapter chip is configured to establish a common physical interface (PHY) for communicating between the first interface circuitry and the second interface circuitry.
11. The MCM of claim 10 , wherein:
the multiple IC chips of the chip stack comprise memory chips.
12. The MCM of claim 10 , wherein:
the chip stack exhibits a footprint of a first surface area; and
the interface adapter chip exhibits a footprint of a second surface area that is less than the first surface area.
13. The MCM of claim 10 , wherein:
the first interface circuitry comprises a first interface chip that is stacked with the chip stack.
14. The MCM of claim 10 , wherein:
the first integrated circuit (IC) chip assembly includes a secondary substrate formed with a mold material that forms a base layer of the first IC chip assembly;
wherein the interface adapter chip is embedded in the secondary substrate; and
wherein the first interface circuitry comprises a first interface chip that is embedded in the secondary substrate and disposed in a horizontal relationship with the interface adapter chip.
15. The MCM of claim 10 , wherein:
the interface adapter chip is encapsulated in a mold material to form a stack base that exhibits a surface area that approximates the first surface area; and
wherein the chip stack is stacked vertically on the stack base.
16. The MCM of claim 15 , further comprising:
a first interface chip, the first interface chip being encapsulated in the mold material and being positioned in a horizontal relationship with the interface adapter chip.
17. The MCM of claim 15 , wherein:
the interface adapter chip includes a first surface that is formed with an active device side;
the interface adapter chip is positioned in the mold material such that the active device layer is positioned proximate the non-silicon substrate;
wherein communication between the interface adapter chip and the chip stack is carried out by through-silicon-vias (TSVs) formed from the chip stack and through the interface adapter chip to the active device side; and
wherein communication between the interface adapter chip and the non-silicon substrate is carried out by direct routing paths from the non-silicon substrate to the active device side.
18. The MCM of claim 17 , wherein:
the interface adapter chip includes a first surface that is formed with an active device side;
the interface adapter chip is positioned in the mold material such that the active device side is positioned proximate the chip stack;
wherein communication between the interface adapter chip and the non-silicon substrate is carried out by through-silicon-vias (TSVs) formed from the non-silicon substrate and through the interface adapter chip to the active device side; and
wherein communication between the interface adapter chip and the chip stack is carried out by direct routing paths from the chip stack to the active device side.